1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <ahci.h> 10 #include <linux/mbus.h> 11 #include <asm/io.h> 12 #include <asm/pl310.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/soc.h> 15 #include <sdhci.h> 16 17 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 18 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 19 20 static struct mbus_win windows[] = { 21 /* SPI */ 22 { MBUS_SPI_BASE, MBUS_SPI_SIZE, 23 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, 24 25 /* NOR */ 26 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, 27 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, 28 }; 29 30 void reset_cpu(unsigned long ignored) 31 { 32 struct mvebu_system_registers *reg = 33 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 34 35 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 36 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 37 while (1) 38 ; 39 } 40 41 int mvebu_soc_family(void) 42 { 43 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 44 45 if (devid == SOC_MV78460_ID) 46 return MVEBU_SOC_AXP; 47 48 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || 49 devid == SOC_88F6828_ID) 50 return MVEBU_SOC_A38X; 51 52 return MVEBU_SOC_UNKNOWN; 53 } 54 55 #if defined(CONFIG_DISPLAY_CPUINFO) 56 int print_cpuinfo(void) 57 { 58 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 59 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 60 61 puts("SoC: "); 62 63 switch (devid) { 64 case SOC_MV78460_ID: 65 puts("MV78460-"); 66 break; 67 case SOC_88F6810_ID: 68 puts("MV88F6810-"); 69 break; 70 case SOC_88F6820_ID: 71 puts("MV88F6820-"); 72 break; 73 case SOC_88F6828_ID: 74 puts("MV88F6828-"); 75 break; 76 default: 77 puts("Unknown-"); 78 break; 79 } 80 81 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 82 switch (revid) { 83 case 1: 84 puts("A0\n"); 85 break; 86 case 2: 87 puts("B0\n"); 88 break; 89 default: 90 printf("?? (%x)\n", revid); 91 break; 92 } 93 } 94 95 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 96 switch (revid) { 97 case MV_88F68XX_Z1_ID: 98 puts("Z1\n"); 99 break; 100 case MV_88F68XX_A0_ID: 101 puts("A0\n"); 102 break; 103 default: 104 printf("?? (%x)\n", revid); 105 break; 106 } 107 } 108 109 return 0; 110 } 111 #endif /* CONFIG_DISPLAY_CPUINFO */ 112 113 /* 114 * This function initialize Controller DRAM Fastpath windows. 115 * It takes the CS size information from the 0x1500 scratch registers 116 * and sets the correct windows sizes and base addresses accordingly. 117 * 118 * These values are set in the scratch registers by the Marvell 119 * DDR3 training code, which is executed by the BootROM before the 120 * main payload (U-Boot) is executed. This training code is currently 121 * only available in the Marvell U-Boot version. It needs to be 122 * ported to mainline U-Boot SPL at some point. 123 */ 124 static void update_sdram_window_sizes(void) 125 { 126 u64 base = 0; 127 u32 size, temp; 128 int i; 129 130 for (i = 0; i < SDRAM_MAX_CS; i++) { 131 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 132 if (size != 0) { 133 size |= ~(SDRAM_ADDR_MASK); 134 135 /* Set Base Address */ 136 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 137 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 138 139 /* 140 * Check if out of max window size and resize 141 * the window 142 */ 143 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 144 ~(SDRAM_ADDR_MASK)) | 1; 145 temp |= (size & SDRAM_ADDR_MASK); 146 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 147 148 base += ((u64)size + 1); 149 } else { 150 /* 151 * Disable window if not used, otherwise this 152 * leads to overlapping enabled windows with 153 * pretty strange results 154 */ 155 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 156 } 157 } 158 } 159 160 void mmu_disable(void) 161 { 162 asm volatile( 163 "mrc p15, 0, r0, c1, c0, 0\n" 164 "bic r0, #1\n" 165 "mcr p15, 0, r0, c1, c0, 0\n"); 166 } 167 168 #ifdef CONFIG_ARCH_CPU_INIT 169 static void set_cbar(u32 addr) 170 { 171 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); 172 } 173 174 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) 175 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) 176 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ 177 (((addr) & 0xF) << 6)) 178 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ 179 (((reg) & 0xF) << 2)) 180 181 static void setup_usb_phys(void) 182 { 183 int dev; 184 185 /* 186 * USB PLL init 187 */ 188 189 /* Setup PLL frequency */ 190 /* USB REF frequency = 25 MHz */ 191 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); 192 193 /* Power up PLL and PHY channel */ 194 clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9)); 195 196 /* Assert VCOCAL_START */ 197 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21)); 198 199 mdelay(1); 200 201 /* 202 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60) 203 */ 204 205 for (dev = 0; dev < 3; dev++) { 206 clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15)); 207 208 /* Assert REG_RCAL_START in channel REG 1 */ 209 clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12)); 210 udelay(40); 211 clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0); 212 } 213 } 214 215 int arch_cpu_init(void) 216 { 217 #ifndef CONFIG_SPL_BUILD 218 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 219 struct pl310_regs *const pl310 = 220 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 221 222 /* 223 * Only with disabled MMU its possible to switch the base 224 * register address on Armada 38x. Without this the SDRAM 225 * located at >= 0x4000.0000 is also not accessible, as its 226 * still locked to cache. 227 * 228 * So to fully release / unlock this area from cache, we need 229 * to first flush all caches, then disable the MMU and 230 * disable the L2 cache. 231 */ 232 icache_disable(); 233 dcache_disable(); 234 mmu_disable(); 235 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 236 } 237 #endif 238 239 /* Linux expects the internal registers to be at 0xf1000000 */ 240 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 241 set_cbar(SOC_REGS_PHY_BASE + 0xC000); 242 243 /* 244 * We need to call mvebu_mbus_probe() before calling 245 * update_sdram_window_sizes() as it disables all previously 246 * configured mbus windows and then configures them as 247 * required for U-Boot. Calling update_sdram_window_sizes() 248 * without this configuration will not work, as the internal 249 * registers can't be accessed reliably because of potenial 250 * double mapping. 251 * After updating the SDRAM access windows we need to call 252 * mvebu_mbus_probe() again, as this now correctly configures 253 * the SDRAM areas that are later used by the MVEBU drivers 254 * (e.g. USB, NETA). 255 */ 256 257 /* 258 * First disable all windows 259 */ 260 mvebu_mbus_probe(NULL, 0); 261 262 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 263 /* 264 * Now the SDRAM access windows can be reconfigured using 265 * the information in the SDRAM scratch pad registers 266 */ 267 update_sdram_window_sizes(); 268 } 269 270 /* 271 * Finally the mbus windows can be configured with the 272 * updated SDRAM sizes 273 */ 274 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 275 276 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 277 /* Enable GBE0, GBE1, LCD and NFC PUP */ 278 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, 279 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | 280 NAND_PUP_EN | SPI_PUP_EN); 281 282 /* Configure USB PLL and PHYs on AXP */ 283 setup_usb_phys(); 284 } 285 286 /* Enable NAND and NAND arbiter */ 287 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN); 288 289 /* Disable MBUS error propagation */ 290 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); 291 292 return 0; 293 } 294 #endif /* CONFIG_ARCH_CPU_INIT */ 295 296 u32 mvebu_get_nand_clock(void) 297 { 298 return CONFIG_SYS_MVEBU_PLL_CLOCK / 299 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) & 300 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); 301 } 302 303 /* 304 * SOC specific misc init 305 */ 306 #if defined(CONFIG_ARCH_MISC_INIT) 307 int arch_misc_init(void) 308 { 309 /* Nothing yet, perhaps we need something here later */ 310 return 0; 311 } 312 #endif /* CONFIG_ARCH_MISC_INIT */ 313 314 #ifdef CONFIG_MVNETA 315 int cpu_eth_init(bd_t *bis) 316 { 317 u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE, 318 MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE }; 319 u8 phy_addr[] = CONFIG_PHY_ADDR; 320 int i; 321 322 /* 323 * Only Armada XP supports all 4 ethernet interfaces. A38x has 324 * slightly different base addresses for its 2-3 interfaces. 325 */ 326 if (mvebu_soc_family() != MVEBU_SOC_AXP) { 327 enet_base[1] = MVEBU_EGIGA2_BASE; 328 enet_base[2] = MVEBU_EGIGA3_BASE; 329 } 330 331 for (i = 0; i < ARRAY_SIZE(phy_addr); i++) 332 mvneta_initialize(bis, enet_base[i], i, phy_addr[i]); 333 334 return 0; 335 } 336 #endif 337 338 #ifdef CONFIG_MV_SDHCI 339 int board_mmc_init(bd_t *bis) 340 { 341 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, 342 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); 343 344 return 0; 345 } 346 #endif 347 348 #ifdef CONFIG_SCSI_AHCI_PLAT 349 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 350 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 351 352 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) 353 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) 354 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) 355 356 static void ahci_mvebu_mbus_config(void __iomem *base) 357 { 358 const struct mbus_dram_target_info *dram; 359 int i; 360 361 dram = mvebu_mbus_dram_info(); 362 363 for (i = 0; i < 4; i++) { 364 writel(0, base + AHCI_WINDOW_CTRL(i)); 365 writel(0, base + AHCI_WINDOW_BASE(i)); 366 writel(0, base + AHCI_WINDOW_SIZE(i)); 367 } 368 369 for (i = 0; i < dram->num_cs; i++) { 370 const struct mbus_dram_window *cs = dram->cs + i; 371 372 writel((cs->mbus_attr << 8) | 373 (dram->mbus_dram_target_id << 4) | 1, 374 base + AHCI_WINDOW_CTRL(i)); 375 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); 376 writel(((cs->size - 1) & 0xffff0000), 377 base + AHCI_WINDOW_SIZE(i)); 378 } 379 } 380 381 static void ahci_mvebu_regret_option(void __iomem *base) 382 { 383 /* 384 * Enable the regret bit to allow the SATA unit to regret a 385 * request that didn't receive an acknowlegde and avoid a 386 * deadlock 387 */ 388 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); 389 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); 390 } 391 392 void scsi_init(void) 393 { 394 printf("MVEBU SATA INIT\n"); 395 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); 396 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); 397 ahci_init((void __iomem *)MVEBU_SATA0_BASE); 398 } 399 #endif 400 401 #ifndef CONFIG_SYS_DCACHE_OFF 402 void enable_caches(void) 403 { 404 struct pl310_regs *const pl310 = 405 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 406 407 /* First disable L2 cache - may still be enable from BootROM */ 408 if (mvebu_soc_family() == MVEBU_SOC_A38X) 409 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 410 411 /* Avoid problem with e.g. neta ethernet driver */ 412 invalidate_dcache_all(); 413 414 /* Enable D-cache. I-cache is already enabled in start.S */ 415 dcache_enable(); 416 } 417 #endif 418