1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <ahci.h> 10 #include <linux/mbus.h> 11 #include <asm/io.h> 12 #include <asm/pl310.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/soc.h> 15 #include <sdhci.h> 16 17 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 18 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 19 20 static struct mbus_win windows[] = { 21 /* PCIE MEM address space */ 22 { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM }, 23 24 /* PCIE IO address space */ 25 { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO }, 26 27 /* SPI */ 28 { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, 29 CPU_ATTR_SPIFLASH }, 30 31 /* NOR */ 32 { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, 33 CPU_ATTR_BOOTROM }, 34 }; 35 36 void reset_cpu(unsigned long ignored) 37 { 38 struct mvebu_system_registers *reg = 39 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 40 41 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 42 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 43 while (1) 44 ; 45 } 46 47 int mvebu_soc_family(void) 48 { 49 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 50 51 if (devid == SOC_MV78460_ID) 52 return MVEBU_SOC_AXP; 53 54 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || 55 devid == SOC_88F6828_ID) 56 return MVEBU_SOC_A38X; 57 58 return MVEBU_SOC_UNKNOWN; 59 } 60 61 #if defined(CONFIG_DISPLAY_CPUINFO) 62 int print_cpuinfo(void) 63 { 64 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 65 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 66 67 puts("SoC: "); 68 69 switch (devid) { 70 case SOC_MV78460_ID: 71 puts("MV78460-"); 72 break; 73 case SOC_88F6810_ID: 74 puts("MV88F6810-"); 75 break; 76 case SOC_88F6820_ID: 77 puts("MV88F6820-"); 78 break; 79 case SOC_88F6828_ID: 80 puts("MV88F6828-"); 81 break; 82 default: 83 puts("Unknown-"); 84 break; 85 } 86 87 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 88 switch (revid) { 89 case 1: 90 puts("A0\n"); 91 break; 92 case 2: 93 puts("B0\n"); 94 break; 95 default: 96 printf("?? (%x)\n", revid); 97 break; 98 } 99 } 100 101 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 102 switch (revid) { 103 case MV_88F68XX_Z1_ID: 104 puts("Z1\n"); 105 break; 106 case MV_88F68XX_A0_ID: 107 puts("A0\n"); 108 break; 109 default: 110 printf("?? (%x)\n", revid); 111 break; 112 } 113 } 114 115 return 0; 116 } 117 #endif /* CONFIG_DISPLAY_CPUINFO */ 118 119 /* 120 * This function initialize Controller DRAM Fastpath windows. 121 * It takes the CS size information from the 0x1500 scratch registers 122 * and sets the correct windows sizes and base addresses accordingly. 123 * 124 * These values are set in the scratch registers by the Marvell 125 * DDR3 training code, which is executed by the BootROM before the 126 * main payload (U-Boot) is executed. This training code is currently 127 * only available in the Marvell U-Boot version. It needs to be 128 * ported to mainline U-Boot SPL at some point. 129 */ 130 static void update_sdram_window_sizes(void) 131 { 132 u64 base = 0; 133 u32 size, temp; 134 int i; 135 136 for (i = 0; i < SDRAM_MAX_CS; i++) { 137 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 138 if (size != 0) { 139 size |= ~(SDRAM_ADDR_MASK); 140 141 /* Set Base Address */ 142 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 143 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 144 145 /* 146 * Check if out of max window size and resize 147 * the window 148 */ 149 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 150 ~(SDRAM_ADDR_MASK)) | 1; 151 temp |= (size & SDRAM_ADDR_MASK); 152 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 153 154 base += ((u64)size + 1); 155 } else { 156 /* 157 * Disable window if not used, otherwise this 158 * leads to overlapping enabled windows with 159 * pretty strange results 160 */ 161 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 162 } 163 } 164 } 165 166 void mmu_disable(void) 167 { 168 asm volatile( 169 "mrc p15, 0, r0, c1, c0, 0\n" 170 "bic r0, #1\n" 171 "mcr p15, 0, r0, c1, c0, 0\n"); 172 } 173 174 #ifdef CONFIG_ARCH_CPU_INIT 175 static void set_cbar(u32 addr) 176 { 177 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); 178 } 179 180 181 int arch_cpu_init(void) 182 { 183 #ifndef CONFIG_SPL_BUILD 184 /* 185 * Only with disabled MMU its possible to switch the base 186 * register address on Armada 38x. Without this the SDRAM 187 * located at >= 0x4000.0000 is also not accessible, as its 188 * still locked to cache. 189 */ 190 mmu_disable(); 191 #endif 192 193 /* Linux expects the internal registers to be at 0xf1000000 */ 194 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 195 set_cbar(SOC_REGS_PHY_BASE + 0xC000); 196 197 /* 198 * We need to call mvebu_mbus_probe() before calling 199 * update_sdram_window_sizes() as it disables all previously 200 * configured mbus windows and then configures them as 201 * required for U-Boot. Calling update_sdram_window_sizes() 202 * without this configuration will not work, as the internal 203 * registers can't be accessed reliably because of potenial 204 * double mapping. 205 * After updating the SDRAM access windows we need to call 206 * mvebu_mbus_probe() again, as this now correctly configures 207 * the SDRAM areas that are later used by the MVEBU drivers 208 * (e.g. USB, NETA). 209 */ 210 211 /* 212 * First disable all windows 213 */ 214 mvebu_mbus_probe(NULL, 0); 215 216 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 217 /* 218 * Now the SDRAM access windows can be reconfigured using 219 * the information in the SDRAM scratch pad registers 220 */ 221 update_sdram_window_sizes(); 222 } 223 224 /* 225 * Finally the mbus windows can be configured with the 226 * updated SDRAM sizes 227 */ 228 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 229 230 return 0; 231 } 232 #endif /* CONFIG_ARCH_CPU_INIT */ 233 234 /* 235 * SOC specific misc init 236 */ 237 #if defined(CONFIG_ARCH_MISC_INIT) 238 int arch_misc_init(void) 239 { 240 /* Nothing yet, perhaps we need something here later */ 241 return 0; 242 } 243 #endif /* CONFIG_ARCH_MISC_INIT */ 244 245 #ifdef CONFIG_MVNETA 246 int cpu_eth_init(bd_t *bis) 247 { 248 u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE, 249 MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE }; 250 u8 phy_addr[] = CONFIG_PHY_ADDR; 251 int i; 252 253 /* 254 * Only Armada XP supports all 4 ethernet interfaces. A38x has 255 * slightly different base addresses for its 2-3 interfaces. 256 */ 257 if (mvebu_soc_family() != MVEBU_SOC_AXP) { 258 enet_base[1] = MVEBU_EGIGA2_BASE; 259 enet_base[2] = MVEBU_EGIGA3_BASE; 260 } 261 262 for (i = 0; i < ARRAY_SIZE(phy_addr); i++) 263 mvneta_initialize(bis, enet_base[i], i, phy_addr[i]); 264 265 return 0; 266 } 267 #endif 268 269 #ifdef CONFIG_MV_SDHCI 270 int board_mmc_init(bd_t *bis) 271 { 272 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, 273 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); 274 275 return 0; 276 } 277 #endif 278 279 #ifdef CONFIG_SCSI_AHCI_PLAT 280 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 281 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 282 283 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) 284 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) 285 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) 286 287 static void ahci_mvebu_mbus_config(void __iomem *base) 288 { 289 const struct mbus_dram_target_info *dram; 290 int i; 291 292 dram = mvebu_mbus_dram_info(); 293 294 for (i = 0; i < 4; i++) { 295 writel(0, base + AHCI_WINDOW_CTRL(i)); 296 writel(0, base + AHCI_WINDOW_BASE(i)); 297 writel(0, base + AHCI_WINDOW_SIZE(i)); 298 } 299 300 for (i = 0; i < dram->num_cs; i++) { 301 const struct mbus_dram_window *cs = dram->cs + i; 302 303 writel((cs->mbus_attr << 8) | 304 (dram->mbus_dram_target_id << 4) | 1, 305 base + AHCI_WINDOW_CTRL(i)); 306 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); 307 writel(((cs->size - 1) & 0xffff0000), 308 base + AHCI_WINDOW_SIZE(i)); 309 } 310 } 311 312 static void ahci_mvebu_regret_option(void __iomem *base) 313 { 314 /* 315 * Enable the regret bit to allow the SATA unit to regret a 316 * request that didn't receive an acknowlegde and avoid a 317 * deadlock 318 */ 319 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); 320 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); 321 } 322 323 void scsi_init(void) 324 { 325 printf("MVEBU SATA INIT\n"); 326 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); 327 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); 328 ahci_init((void __iomem *)MVEBU_SATA0_BASE); 329 } 330 #endif 331 332 #ifndef CONFIG_SYS_DCACHE_OFF 333 void enable_caches(void) 334 { 335 struct pl310_regs *const pl310 = 336 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 337 338 /* First disable L2 cache - may still be enable from BootROM */ 339 if (mvebu_soc_family() == MVEBU_SOC_A38X) 340 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 341 342 /* Avoid problem with e.g. neta ethernet driver */ 343 invalidate_dcache_all(); 344 345 /* Enable D-cache. I-cache is already enabled in start.S */ 346 dcache_enable(); 347 } 348 #endif 349