1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4  */
5 
6 #include <common.h>
7 #include <dm.h>
8 #include <fdtdec.h>
9 #include <linux/libfdt.h>
10 #include <asm/io.h>
11 #include <asm/system.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <asm/armv8/mmu.h>
15 
16 /* Armada 7k/8k */
17 #define MVEBU_RFU_BASE			(MVEBU_REGISTER(0x6f0000))
18 #define RFU_GLOBAL_SW_RST		(MVEBU_RFU_BASE + 0x84)
19 #define RFU_SW_RESET_OFFSET		0
20 
21 #define SAR0_REG			(MVEBU_REGISTER(0x2400200))
22 #define BOOT_MODE_MASK			0x3f
23 #define BOOT_MODE_OFFSET		4
24 
25 /*
26  * The following table includes all memory regions for Armada 7k and
27  * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
28  * define these regions at the beginning of the struct so that they
29  * can be easier removed later dynamically if an Armada 7k device is detected.
30  * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
31  */
32 #define ARMADA_7K8K_COMMON_REGIONS_START	2
33 static struct mm_region mvebu_mem_map[] = {
34 	/* Armada 80x0 memory regions include the CP1 (slave) units */
35 	{
36 		/* SRAM, MMIO regions - CP110 slave region */
37 		.phys = 0xf4000000UL,
38 		.virt = 0xf4000000UL,
39 		.size = 0x02000000UL,	/* 32MiB internal registers */
40 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
41 			 PTE_BLOCK_NON_SHARE
42 	},
43 	{
44 		/* PCI CP1 regions */
45 		.phys = 0xfa000000UL,
46 		.virt = 0xfa000000UL,
47 		.size = 0x04000000UL,	/* 64MiB CP110 slave PCI space */
48 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
49 			 PTE_BLOCK_NON_SHARE
50 	},
51 	/* Armada 80x0 and 70x0 common memory regions start here */
52 	{
53 		/* RAM */
54 		.phys = 0x0UL,
55 		.virt = 0x0UL,
56 		.size = 0x80000000UL,
57 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
58 			 PTE_BLOCK_INNER_SHARE
59 	},
60 	{
61 		/* SRAM, MMIO regions - AP806 region */
62 		.phys = 0xf0000000UL,
63 		.virt = 0xf0000000UL,
64 		.size = 0x01000000UL,	/* 16MiB internal registers */
65 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
66 			 PTE_BLOCK_NON_SHARE
67 	},
68 	{
69 		/* SRAM, MMIO regions - CP110 master region */
70 		.phys = 0xf2000000UL,
71 		.virt = 0xf2000000UL,
72 		.size = 0x02000000UL,	/* 32MiB internal registers */
73 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
74 			 PTE_BLOCK_NON_SHARE
75 	},
76 	{
77 		/* PCI CP0 regions */
78 		.phys = 0xf6000000UL,
79 		.virt = 0xf6000000UL,
80 		.size = 0x04000000UL,	/* 64MiB CP110 master PCI space */
81 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
82 			 PTE_BLOCK_NON_SHARE
83 	},
84 	{
85 		0,
86 	}
87 };
88 
89 struct mm_region *mem_map = mvebu_mem_map;
90 
91 void enable_caches(void)
92 {
93 	/*
94 	 * Armada 7k is not equipped with the CP110 slave CP. In case this
95 	 * code runs on an Armada 7k device, lets remove the CP110 slave
96 	 * entries from the memory mapping by moving the start to the
97 	 * common regions.
98 	 */
99 	if (of_machine_is_compatible("marvell,armada7040"))
100 		mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
101 
102 	icache_enable();
103 	dcache_enable();
104 }
105 
106 void reset_cpu(ulong ignored)
107 {
108 	u32 reg;
109 
110 	reg = readl(RFU_GLOBAL_SW_RST);
111 	reg &= ~(1 << RFU_SW_RESET_OFFSET);
112 	writel(reg, RFU_GLOBAL_SW_RST);
113 }
114 
115 /*
116  * TODO - implement this functionality using platform
117  *        clock driver once it gets available
118  * Return NAND clock in Hz
119  */
120 u32 mvebu_get_nand_clock(void)
121 {
122 	unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
123 	unsigned long NF_CLOCK_SEL_MASK = 0x1;
124 	u32 reg;
125 
126 	reg = readl(NAND_FLASH_CLK_CTRL);
127 	if (reg & NF_CLOCK_SEL_MASK)
128 		return 400 * 1000000;
129 	else
130 		return 250 * 1000000;
131 }
132 
133 int mmc_get_env_dev(void)
134 {
135 	u32 reg;
136 	unsigned int boot_mode;
137 
138 	reg = readl(SAR0_REG);
139 	boot_mode = (reg >> BOOT_MODE_OFFSET) & BOOT_MODE_MASK;
140 
141 	switch (boot_mode) {
142 	case 0x28:
143 	case 0x2a:
144 		return 0;
145 	case 0x29:
146 	case 0x2b:
147 		return 1;
148 	}
149 
150 	return CONFIG_SYS_MMC_ENV_DEV;
151 }
152