1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4  */
5 
6 #include <common.h>
7 #include <dm.h>
8 #include <fdtdec.h>
9 #include <linux/libfdt.h>
10 #include <asm/io.h>
11 #include <asm/system.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <asm/armv8/mmu.h>
15 
16 /* Armada 7k/8k */
17 #define MVEBU_RFU_BASE			(MVEBU_REGISTER(0x6f0000))
18 #define RFU_GLOBAL_SW_RST		(MVEBU_RFU_BASE + 0x84)
19 #define RFU_SW_RESET_OFFSET		0
20 
21 /*
22  * The following table includes all memory regions for Armada 7k and
23  * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
24  * define these regions at the beginning of the struct so that they
25  * can be easier removed later dynamically if an Armada 7k device is detected.
26  * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
27  */
28 #define ARMADA_7K8K_COMMON_REGIONS_START	2
29 static struct mm_region mvebu_mem_map[] = {
30 	/* Armada 80x0 memory regions include the CP1 (slave) units */
31 	{
32 		/* SRAM, MMIO regions - CP110 slave region */
33 		.phys = 0xf4000000UL,
34 		.virt = 0xf4000000UL,
35 		.size = 0x02000000UL,	/* 32MiB internal registers */
36 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
37 			 PTE_BLOCK_NON_SHARE
38 	},
39 	{
40 		/* PCI CP1 regions */
41 		.phys = 0xfa000000UL,
42 		.virt = 0xfa000000UL,
43 		.size = 0x04000000UL,	/* 64MiB CP110 slave PCI space */
44 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
45 			 PTE_BLOCK_NON_SHARE
46 	},
47 	/* Armada 80x0 and 70x0 common memory regions start here */
48 	{
49 		/* RAM */
50 		.phys = 0x0UL,
51 		.virt = 0x0UL,
52 		.size = 0x80000000UL,
53 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
54 			 PTE_BLOCK_INNER_SHARE
55 	},
56 	{
57 		/* SRAM, MMIO regions - AP806 region */
58 		.phys = 0xf0000000UL,
59 		.virt = 0xf0000000UL,
60 		.size = 0x01000000UL,	/* 16MiB internal registers */
61 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
62 			 PTE_BLOCK_NON_SHARE
63 	},
64 	{
65 		/* SRAM, MMIO regions - CP110 master region */
66 		.phys = 0xf2000000UL,
67 		.virt = 0xf2000000UL,
68 		.size = 0x02000000UL,	/* 32MiB internal registers */
69 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
70 			 PTE_BLOCK_NON_SHARE
71 	},
72 	{
73 		/* PCI CP0 regions */
74 		.phys = 0xf6000000UL,
75 		.virt = 0xf6000000UL,
76 		.size = 0x04000000UL,	/* 64MiB CP110 master PCI space */
77 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
78 			 PTE_BLOCK_NON_SHARE
79 	},
80 	{
81 		0,
82 	}
83 };
84 
85 struct mm_region *mem_map = mvebu_mem_map;
86 
87 void enable_caches(void)
88 {
89 	/*
90 	 * Armada 7k is not equipped with the CP110 slave CP. In case this
91 	 * code runs on an Armada 7k device, lets remove the CP110 slave
92 	 * entries from the memory mapping by moving the start to the
93 	 * common regions.
94 	 */
95 	if (of_machine_is_compatible("marvell,armada7040"))
96 		mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
97 
98 	icache_enable();
99 	dcache_enable();
100 }
101 
102 void reset_cpu(ulong ignored)
103 {
104 	u32 reg;
105 
106 	reg = readl(RFU_GLOBAL_SW_RST);
107 	reg &= ~(1 << RFU_SW_RESET_OFFSET);
108 	writel(reg, RFU_GLOBAL_SW_RST);
109 }
110 
111 /*
112  * TODO - implement this functionality using platform
113  *        clock driver once it gets available
114  * Return NAND clock in Hz
115  */
116 u32 mvebu_get_nand_clock(void)
117 {
118 	unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
119 	unsigned long NF_CLOCK_SEL_MASK = 0x1;
120 	u32 reg;
121 
122 	reg = readl(NAND_FLASH_CLK_CTRL);
123 	if (reg & NF_CLOCK_SEL_MASK)
124 		return 400 * 1000000;
125 	else
126 		return 250 * 1000000;
127 }
128