1 /*
2  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <libfdt.h>
11 #include <asm/io.h>
12 #include <asm/system.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <asm/armv8/mmu.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 /* Armada 7k/8k */
20 #define MVEBU_RFU_BASE			(MVEBU_REGISTER(0x6f0000))
21 #define RFU_GLOBAL_SW_RST		(MVEBU_RFU_BASE + 0x84)
22 #define RFU_SW_RESET_OFFSET		0
23 
24 static struct mm_region mvebu_mem_map[] = {
25 	{
26 		/* RAM */
27 		.phys = 0x0UL,
28 		.virt = 0x0UL,
29 		.size = 0x80000000UL,
30 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
31 			 PTE_BLOCK_INNER_SHARE
32 	},
33 	{
34 		/* SRAM, MMIO regions - AP806 region */
35 		.phys = 0xf0000000UL,
36 		.virt = 0xf0000000UL,
37 		.size = 0x01000000UL,	/* 16MiB internal registers */
38 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
39 			 PTE_BLOCK_NON_SHARE
40 	},
41 	{
42 		/* SRAM, MMIO regions - CP110 master region */
43 		.phys = 0xf2000000UL,
44 		.virt = 0xf2000000UL,
45 		.size = 0x02000000UL,	/* 32MiB internal registers */
46 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
47 			 PTE_BLOCK_NON_SHARE
48 	},
49 	{
50 		/* SRAM, MMIO regions - CP110 slave region */
51 		.phys = 0xf4000000UL,
52 		.virt = 0xf4000000UL,
53 		.size = 0x02000000UL,	/* 32MiB internal registers */
54 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
55 			 PTE_BLOCK_NON_SHARE
56 	},
57 	{
58 		/* PCI regions */
59 		.phys = 0xf8000000UL,
60 		.virt = 0xf8000000UL,
61 		.size = 0x08000000UL,	/* 128MiB PCI space (master & slave) */
62 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
63 			 PTE_BLOCK_NON_SHARE
64 	},
65 	{
66 		/* List terminator */
67 		0,
68 	}
69 };
70 
71 struct mm_region *mem_map = mvebu_mem_map;
72 
73 void reset_cpu(ulong ignored)
74 {
75 	u32 reg;
76 
77 	reg = readl(RFU_GLOBAL_SW_RST);
78 	reg &= ~(1 << RFU_SW_RESET_OFFSET);
79 	writel(reg, RFU_GLOBAL_SW_RST);
80 }
81