1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <fdtdec.h> 9 #include <linux/libfdt.h> 10 #include <asm/io.h> 11 #include <asm/system.h> 12 #include <asm/arch/cpu.h> 13 #include <asm/arch/soc.h> 14 #include <asm/armv8/mmu.h> 15 16 /* Armada 3700 */ 17 #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800)) 18 19 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8) 20 #define MVEBU_XTAL_MODE_MASK BIT(9) 21 #define MVEBU_XTAL_MODE_OFFS 9 22 #define MVEBU_XTAL_CLOCK_25MHZ 0x0 23 #define MVEBU_XTAL_CLOCK_40MHZ 0x1 24 25 #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40) 26 #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e 27 28 static struct mm_region mvebu_mem_map[] = { 29 { 30 /* RAM */ 31 .phys = 0x0UL, 32 .virt = 0x0UL, 33 .size = 0x80000000UL, 34 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 35 PTE_BLOCK_INNER_SHARE 36 }, 37 { 38 /* SRAM, MMIO regions */ 39 .phys = 0xd0000000UL, 40 .virt = 0xd0000000UL, 41 .size = 0x02000000UL, /* 32MiB internal registers */ 42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 43 PTE_BLOCK_NON_SHARE 44 }, 45 { 46 /* PCI regions */ 47 .phys = 0xe8000000UL, 48 .virt = 0xe8000000UL, 49 .size = 0x02000000UL, /* 32MiB master PCI space */ 50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 51 PTE_BLOCK_NON_SHARE 52 }, 53 { 54 /* List terminator */ 55 0, 56 } 57 }; 58 59 struct mm_region *mem_map = mvebu_mem_map; 60 61 void reset_cpu(ulong ignored) 62 { 63 /* 64 * Write magic number of 0x1d1e to North Bridge Warm Reset register 65 * to trigger warm reset 66 */ 67 writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG); 68 } 69 70 /* 71 * get_ref_clk 72 * 73 * return: reference clock in MHz (25 or 40) 74 */ 75 u32 get_ref_clk(void) 76 { 77 u32 regval; 78 79 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> 80 MVEBU_XTAL_MODE_OFFS; 81 82 if (regval == MVEBU_XTAL_CLOCK_25MHZ) 83 return 25; 84 else 85 return 40; 86 } 87