1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> 4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7 #include <common.h> 8 #include <asm/arch/boot.h> 9 #include <asm/arch/eth.h> 10 #include <asm/arch/gx.h> 11 #include <asm/arch/mem.h> 12 #include <asm/io.h> 13 #include <asm/armv8/mmu.h> 14 #include <linux/sizes.h> 15 #include <phy.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 int meson_get_boot_device(void) 20 { 21 return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE; 22 } 23 24 /* Configure the reserved memory zones exported by the secure registers 25 * into EFI and DTB reserved memory entries. 26 */ 27 void meson_init_reserved_memory(void *fdt) 28 { 29 u64 bl31_size, bl31_start; 30 u64 bl32_size, bl32_start; 31 u32 reg; 32 33 /* 34 * Get ARM Trusted Firmware reserved memory zones in : 35 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 36 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL 37 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL 38 */ 39 reg = readl(GX_AO_SEC_GP_CFG3); 40 41 bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK) 42 >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; 43 bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; 44 45 bl31_start = readl(GX_AO_SEC_GP_CFG5); 46 bl32_start = readl(GX_AO_SEC_GP_CFG4); 47 48 /* 49 * Early Meson GX Firmware revisions did not provide the reserved 50 * memory zones in the registers, keep fixed memory zone handling. 51 */ 52 if (IS_ENABLED(CONFIG_MESON_GX) && 53 !reg && !bl31_start && !bl32_start) { 54 bl31_start = 0x10000000; 55 bl31_size = 0x200000; 56 } 57 58 /* Add first 16MiB reserved zone */ 59 meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE); 60 61 /* Add BL31 reserved zone */ 62 if (bl31_start && bl31_size) 63 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); 64 65 /* Add BL32 reserved zone */ 66 if (bl32_start && bl32_size) 67 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); 68 } 69 70 phys_size_t get_effective_memsize(void) 71 { 72 /* Size is reported in MiB, convert it in bytes */ 73 return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK) 74 >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M; 75 } 76 77 static struct mm_region gx_mem_map[] = { 78 { 79 .virt = 0x0UL, 80 .phys = 0x0UL, 81 .size = 0xc0000000UL, 82 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 83 PTE_BLOCK_INNER_SHARE 84 }, { 85 .virt = 0xc0000000UL, 86 .phys = 0xc0000000UL, 87 .size = 0x30000000UL, 88 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 89 PTE_BLOCK_NON_SHARE | 90 PTE_BLOCK_PXN | PTE_BLOCK_UXN 91 }, { 92 /* List terminator */ 93 0, 94 } 95 }; 96 97 struct mm_region *mem_map = gx_mem_map; 98 99 /* Configure the Ethernet MAC with the requested interface mode 100 * with some optional flags. 101 */ 102 void meson_eth_init(phy_interface_t mode, unsigned int flags) 103 { 104 switch (mode) { 105 case PHY_INTERFACE_MODE_RGMII: 106 case PHY_INTERFACE_MODE_RGMII_ID: 107 case PHY_INTERFACE_MODE_RGMII_RXID: 108 case PHY_INTERFACE_MODE_RGMII_TXID: 109 /* Set RGMII mode */ 110 setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | 111 GX_ETH_REG_0_TX_PHASE(1) | 112 GX_ETH_REG_0_TX_RATIO(4) | 113 GX_ETH_REG_0_PHY_CLK_EN | 114 GX_ETH_REG_0_CLK_EN); 115 break; 116 117 case PHY_INTERFACE_MODE_RMII: 118 /* Set RMII mode */ 119 out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | 120 GX_ETH_REG_0_CLK_EN); 121 122 /* Use GXL RMII Internal PHY */ 123 if (IS_ENABLED(CONFIG_MESON_GXL) && 124 (flags & MESON_USE_INTERNAL_RMII_PHY)) { 125 writel(0x10110181, GX_ETH_REG_2); 126 writel(0xe40908ff, GX_ETH_REG_3); 127 } 128 129 break; 130 131 default: 132 printf("Invalid Ethernet interface mode\n"); 133 return; 134 } 135 136 /* Enable power gate */ 137 clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); 138 } 139