1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 */
5
6#include <linux/linkage.h>
7
8ENTRY(lowlevel_init)
9
10#ifndef CONFIG_SPL_BUILD
11	/* Return to U-Boot via saved link register */
12	mov	pc, lr
13#else
14	/*
15	 * Arch timer :
16	 * set CNTFRQ = 20Mhz, set CNTVOFF = 0
17	 */
18	movw	r0, #0x2d00
19	movt	r0, #0x131
20	mcr	p15, 0, r0, c14, c0, 0
21
22	/* enable SMP bit */
23	mrc	p15, 0, r0, c1, c0, 1
24	orr	r0, r0, #0x40
25	mcr	p15, 0, r0, c1, c0, 1
26
27	/* if MP core, handle secondary cores */
28	mrc	p15, 0, r0, c0, c0, 5
29	ands	r1, r0, #0x40000000
30	bne	go			@ Go if UP
31	ands	r0, r0, #0x0f
32	beq	go			@ Go if core0 on primary core tile
33	b	secondary
34
35go:
36	/* master CPU */
37	mov	pc, lr
38
39secondary:
40	/* read slave CPU number into r0 firstly */
41	mrc	p15, 0, r0, c0, c0, 5
42	and	r0, r0, #0x0f
43
44loop:
45	dsb
46	isb
47	wfi				@Zzz...
48	b	loop
49#endif
50ENDPROC(lowlevel_init)
51