1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 MediaTek Inc.
4  * Author: Ryder Lee <ryder.lee@mediatek.com>
5  */
6 
7 #include <clk.h>
8 #include <common.h>
9 #include <dm.h>
10 #include <fdtdec.h>
11 #include <ram.h>
12 #include <asm/arch/misc.h>
13 #include <asm/sections.h>
14 #include <dm/uclass.h>
15 #include <linux/io.h>
16 
17 #include <dt-bindings/clock/mt7629-clk.h>
18 
19 #define L2_CFG_BASE		0x10200000
20 #define L2_CFG_SIZE		0x1000
21 #define L2_SHARE_CFG_MP0	0x7f0
22 #define L2_SHARE_MODE_OFF	BIT(8)
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 int mtk_pll_early_init(void)
27 {
28 	unsigned long pll_rates[] = {
29 		[CLK_APMIXED_ARMPLL] = 1250000000,
30 		[CLK_APMIXED_MAINPLL] = 1120000000,
31 		[CLK_APMIXED_UNIV2PLL] = 1200000000,
32 		[CLK_APMIXED_ETH1PLL] = 500000000,
33 		[CLK_APMIXED_ETH2PLL] = 700000000,
34 		[CLK_APMIXED_SGMIPLL] = 650000000,
35 	};
36 	struct udevice *dev;
37 	int ret, i;
38 
39 	ret = uclass_get_device_by_driver(UCLASS_CLK,
40 			DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
41 	if (ret)
42 		return ret;
43 
44 	/* configure default rate then enable apmixedsys */
45 	for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
46 		struct clk clk = { .id = i, .dev = dev };
47 
48 		ret = clk_set_rate(&clk, pll_rates[i]);
49 		if (ret)
50 			return ret;
51 
52 		ret = clk_enable(&clk);
53 		if (ret)
54 			return ret;
55 	}
56 
57 	/* setup mcu bus */
58 	ret = uclass_get_device_by_driver(UCLASS_SYSCON,
59 			DM_GET_DRIVER(mtk_mcucfg), &dev);
60 	if (ret)
61 		return ret;
62 
63 	return 0;
64 }
65 
66 int mtk_soc_early_init(void)
67 {
68 	struct udevice *dev;
69 	int ret;
70 
71 	/* initialize early clocks */
72 	ret = mtk_pll_early_init();
73 	if (ret)
74 		return ret;
75 
76 	ret = uclass_first_device_err(UCLASS_RAM, &dev);
77 	if (ret)
78 		return ret;
79 
80 	return 0;
81 }
82 
83 int mach_cpu_init(void)
84 {
85 	void __iomem *base;
86 
87 	base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
88 
89 	/* disable L2C shared mode */
90 	writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
91 
92 	return 0;
93 }
94 
95 int dram_init(void)
96 {
97 	struct ram_info ram;
98 	struct udevice *dev;
99 	int ret;
100 
101 	ret = uclass_first_device_err(UCLASS_RAM, &dev);
102 	if (ret)
103 		return ret;
104 
105 	ret = ram_get_info(dev, &ram);
106 	if (ret)
107 		return ret;
108 
109 	debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
110 
111 	gd->ram_size = ram.size;
112 
113 	return 0;
114 }
115 
116 int print_cpuinfo(void)
117 {
118 	void __iomem *chipid;
119 	u32 hwcode, swver;
120 
121 	chipid = ioremap(VER_BASE, VER_SIZE);
122 	hwcode = readl(chipid + APHW_CODE);
123 	swver = readl(chipid + APSW_VER);
124 
125 	printf("CPU:   MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
126 
127 	return 0;
128 }
129