1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2011 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Lei Wen <leiwen@marvell.com> 6 */ 7 8 /* 9 * This file should be included in board config header file. 10 * 11 * It supports common definitions for Kirkwood platform 12 */ 13 14 #ifndef _KW_CONFIG_H 15 #define _KW_CONFIG_H 16 17 #if defined (CONFIG_KW88F6281) 18 #include <asm/arch/kw88f6281.h> 19 #elif defined (CONFIG_KW88F6192) 20 #include <asm/arch/kw88f6192.h> 21 #else 22 #error "SOC Name not defined" 23 #endif /* CONFIG_KW88F6281 */ 24 25 #include <asm/arch/soc.h> 26 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ 27 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ 28 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ 29 30 /* 31 * By default kwbimage.cfg from board specific folder is used 32 * If for some board, different configuration file need to be used, 33 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 34 */ 35 #ifndef CONFIG_SYS_KWD_CONFIG 36 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg 37 #endif /* CONFIG_SYS_KWD_CONFIG */ 38 39 /* Kirkwood has 2k of Security SRAM, use it for SP */ 40 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 41 #define CONFIG_NR_DRAM_BANKS_MAX 2 42 43 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE 44 #define MV_UART_CONSOLE_BASE KW_UART0_BASE 45 #define MV_SATA_BASE KW_SATA_BASE 46 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET 47 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET 48 49 /* 50 * NAND configuration 51 */ 52 #ifdef CONFIG_CMD_NAND 53 #define CONFIG_NAND_KIRKWOOD 54 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ 55 #define NAND_ALLOW_ERASE_ALL 1 56 #endif 57 58 /* 59 * SPI Flash configuration 60 */ 61 #ifdef CONFIG_CMD_SF 62 #define CONFIG_HARD_SPI 1 63 #ifndef CONFIG_ENV_SPI_BUS 64 # define CONFIG_ENV_SPI_BUS 0 65 #endif 66 #ifndef CONFIG_ENV_SPI_CS 67 # define CONFIG_ENV_SPI_CS 0 68 #endif 69 #ifndef CONFIG_ENV_SPI_MAX_HZ 70 # define CONFIG_ENV_SPI_MAX_HZ 50000000 71 #endif 72 #endif 73 74 /* 75 * Ethernet Driver configuration 76 */ 77 #ifdef CONFIG_CMD_NET 78 #define CONFIG_NETCONSOLE /* include NetConsole support */ 79 #define CONFIG_MII /* expose smi ove miiphy interface */ 80 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 81 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 82 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 83 #endif /* CONFIG_CMD_NET */ 84 85 /* 86 * USB/EHCI 87 */ 88 #ifdef CONFIG_CMD_USB 89 #define CONFIG_EHCI_IS_TDI 90 #endif /* CONFIG_CMD_USB */ 91 92 /* 93 * IDE Support on SATA ports 94 */ 95 #ifdef CONFIG_IDE 96 #define __io 97 #define CONFIG_IDE_PREINIT 98 #define CONFIG_MVSATA_IDE_USE_PORT1 99 /* Needs byte-swapping for ATA data register */ 100 #define CONFIG_IDE_SWAP_IO 101 /* Data, registers and alternate blocks are at the same offset */ 102 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 103 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 104 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 105 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 106 #define CONFIG_SYS_ATA_STRIDE 4 107 /* Controller supports 48-bits LBA addressing */ 108 #define CONFIG_LBA48 109 /* CONFIG_IDE requires some #defines for ATA registers */ 110 #define CONFIG_SYS_IDE_MAXBUS 2 111 #define CONFIG_SYS_IDE_MAXDEVICE 2 112 /* ATA registers base is at SATA controller base */ 113 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE 114 #endif /* CONFIG_IDE */ 115 116 /* 117 * I2C related stuff 118 */ 119 #ifdef CONFIG_CMD_I2C 120 #ifndef CONFIG_SYS_I2C_SOFT 121 #define CONFIG_SYS_I2C 122 #define CONFIG_SYS_I2C_MVTWSI 123 #endif 124 #define CONFIG_SYS_I2C_SLAVE 0x0 125 #define CONFIG_SYS_I2C_SPEED 100000 126 #endif 127 128 /* Use common timer */ 129 #define CONFIG_SYS_TIMER_COUNTS_DOWN 130 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) 131 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK 132 133 #endif /* _KW_CONFIG_H */ 134