1 /* 2 * (C) Copyright 2011 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Lei Wen <leiwen@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * This file should be included in board config header file. 11 * 12 * It supports common definitions for Kirkwood platform 13 */ 14 15 #ifndef _KW_CONFIG_H 16 #define _KW_CONFIG_H 17 18 #if defined (CONFIG_KW88F6281) 19 #include <asm/arch/kw88f6281.h> 20 #elif defined (CONFIG_KW88F6192) 21 #include <asm/arch/kw88f6192.h> 22 #else 23 #error "SOC Name not defined" 24 #endif /* CONFIG_KW88F6281 */ 25 26 #include <asm/arch/soc.h> 27 #define CONFIG_SYS_CACHELINE_SIZE 32 28 /* default Dcache Line length for kirkwood */ 29 #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ 30 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ 31 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ 32 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ 33 34 /* 35 * By default kwbimage.cfg from board specific folder is used 36 * If for some board, different configuration file need to be used, 37 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 38 */ 39 #ifndef CONFIG_SYS_KWD_CONFIG 40 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg 41 #endif /* CONFIG_SYS_KWD_CONFIG */ 42 43 /* Kirkwood has 2k of Security SRAM, use it for SP */ 44 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 45 #define CONFIG_NR_DRAM_BANKS_MAX 2 46 47 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE 48 #define MV_UART_CONSOLE_BASE KW_UART0_BASE 49 #define MV_SATA_BASE KW_SATA_BASE 50 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET 51 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET 52 53 /* 54 * NAND configuration 55 */ 56 #ifdef CONFIG_CMD_NAND 57 #define CONFIG_NAND_KIRKWOOD 58 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ 59 #define NAND_ALLOW_ERASE_ALL 1 60 #endif 61 62 /* 63 * SPI Flash configuration 64 */ 65 #ifdef CONFIG_CMD_SF 66 #define CONFIG_HARD_SPI 1 67 #define CONFIG_KIRKWOOD_SPI 1 68 #ifndef CONFIG_ENV_SPI_BUS 69 # define CONFIG_ENV_SPI_BUS 0 70 #endif 71 #ifndef CONFIG_ENV_SPI_CS 72 # define CONFIG_ENV_SPI_CS 0 73 #endif 74 #ifndef CONFIG_ENV_SPI_MAX_HZ 75 # define CONFIG_ENV_SPI_MAX_HZ 50000000 76 #endif 77 #endif 78 79 /* 80 * Ethernet Driver configuration 81 */ 82 #ifdef CONFIG_CMD_NET 83 #define CONFIG_NETCONSOLE /* include NetConsole support */ 84 #define CONFIG_MII /* expose smi ove miiphy interface */ 85 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ 86 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 87 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 88 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 89 #endif /* CONFIG_CMD_NET */ 90 91 /* 92 * USB/EHCI 93 */ 94 #ifdef CONFIG_CMD_USB 95 #define CONFIG_USB_EHCI_MARVELL 96 #define CONFIG_EHCI_IS_TDI 97 #endif /* CONFIG_CMD_USB */ 98 99 /* 100 * IDE Support on SATA ports 101 */ 102 #ifdef CONFIG_CMD_IDE 103 #define __io 104 #define CONFIG_MVSATA_IDE 105 #define CONFIG_IDE_PREINIT 106 #define CONFIG_MVSATA_IDE_USE_PORT1 107 /* Needs byte-swapping for ATA data register */ 108 #define CONFIG_IDE_SWAP_IO 109 /* Data, registers and alternate blocks are at the same offset */ 110 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 111 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 112 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 113 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 114 #define CONFIG_SYS_ATA_STRIDE 4 115 /* Controller supports 48-bits LBA addressing */ 116 #define CONFIG_LBA48 117 /* CONFIG_CMD_IDE requires some #defines for ATA registers */ 118 #define CONFIG_SYS_IDE_MAXBUS 2 119 #define CONFIG_SYS_IDE_MAXDEVICE 2 120 /* ATA registers base is at SATA controller base */ 121 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE 122 #endif /* CONFIG_CMD_IDE */ 123 124 /* 125 * I2C related stuff 126 */ 127 #ifdef CONFIG_CMD_I2C 128 #ifndef CONFIG_SYS_I2C_SOFT 129 #define CONFIG_SYS_I2C 130 #define CONFIG_SYS_I2C_MVTWSI 131 #endif 132 #define CONFIG_SYS_I2C_SLAVE 0x0 133 #define CONFIG_SYS_I2C_SPEED 100000 134 #endif 135 136 /* Use common timer */ 137 #define CONFIG_SYS_TIMER_COUNTS_DOWN 138 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) 139 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK 140 141 #endif /* _KW_CONFIG_H */ 142