1 /* 2 * (C) Copyright 2011 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Lei Wen <leiwen@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * This file should be included in board config header file. 11 * 12 * It supports common definitions for Kirkwood platform 13 */ 14 15 #ifndef _KW_CONFIG_H 16 #define _KW_CONFIG_H 17 18 #if defined (CONFIG_KW88F6281) 19 #include <asm/arch/kw88f6281.h> 20 #elif defined (CONFIG_KW88F6192) 21 #include <asm/arch/kw88f6192.h> 22 #else 23 #error "SOC Name not defined" 24 #endif /* CONFIG_KW88F6281 */ 25 26 #include <asm/arch/soc.h> 27 #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ 28 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ 29 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ 30 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ 31 32 /* 33 * By default kwbimage.cfg from board specific folder is used 34 * If for some board, different configuration file need to be used, 35 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 36 */ 37 #ifndef CONFIG_SYS_KWD_CONFIG 38 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg 39 #endif /* CONFIG_SYS_KWD_CONFIG */ 40 41 /* Kirkwood has 2k of Security SRAM, use it for SP */ 42 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 43 #define CONFIG_NR_DRAM_BANKS_MAX 2 44 45 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE 46 #define MV_UART_CONSOLE_BASE KW_UART0_BASE 47 #define MV_SATA_BASE KW_SATA_BASE 48 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET 49 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET 50 51 /* 52 * NAND configuration 53 */ 54 #ifdef CONFIG_CMD_NAND 55 #define CONFIG_NAND_KIRKWOOD 56 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ 57 #define NAND_ALLOW_ERASE_ALL 1 58 #endif 59 60 /* 61 * SPI Flash configuration 62 */ 63 #ifdef CONFIG_CMD_SF 64 #define CONFIG_HARD_SPI 1 65 #define CONFIG_KIRKWOOD_SPI 1 66 #ifndef CONFIG_ENV_SPI_BUS 67 # define CONFIG_ENV_SPI_BUS 0 68 #endif 69 #ifndef CONFIG_ENV_SPI_CS 70 # define CONFIG_ENV_SPI_CS 0 71 #endif 72 #ifndef CONFIG_ENV_SPI_MAX_HZ 73 # define CONFIG_ENV_SPI_MAX_HZ 50000000 74 #endif 75 #endif 76 77 /* 78 * Ethernet Driver configuration 79 */ 80 #ifdef CONFIG_CMD_NET 81 #define CONFIG_NETCONSOLE /* include NetConsole support */ 82 #define CONFIG_MII /* expose smi ove miiphy interface */ 83 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ 84 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 85 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 86 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 87 #endif /* CONFIG_CMD_NET */ 88 89 /* 90 * USB/EHCI 91 */ 92 #ifdef CONFIG_CMD_USB 93 #define CONFIG_USB_EHCI_MARVELL 94 #define CONFIG_EHCI_IS_TDI 95 #endif /* CONFIG_CMD_USB */ 96 97 /* 98 * IDE Support on SATA ports 99 */ 100 #ifdef CONFIG_CMD_IDE 101 #define __io 102 #define CONFIG_MVSATA_IDE 103 #define CONFIG_IDE_PREINIT 104 #define CONFIG_MVSATA_IDE_USE_PORT1 105 /* Needs byte-swapping for ATA data register */ 106 #define CONFIG_IDE_SWAP_IO 107 /* Data, registers and alternate blocks are at the same offset */ 108 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 109 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 110 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 111 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 112 #define CONFIG_SYS_ATA_STRIDE 4 113 /* Controller supports 48-bits LBA addressing */ 114 #define CONFIG_LBA48 115 /* CONFIG_CMD_IDE requires some #defines for ATA registers */ 116 #define CONFIG_SYS_IDE_MAXBUS 2 117 #define CONFIG_SYS_IDE_MAXDEVICE 2 118 /* ATA registers base is at SATA controller base */ 119 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE 120 #endif /* CONFIG_CMD_IDE */ 121 122 /* 123 * I2C related stuff 124 */ 125 #ifdef CONFIG_CMD_I2C 126 #ifndef CONFIG_SYS_I2C_SOFT 127 #define CONFIG_SYS_I2C 128 #define CONFIG_SYS_I2C_MVTWSI 129 #endif 130 #define CONFIG_SYS_I2C_SLAVE 0x0 131 #define CONFIG_SYS_I2C_SPEED 100000 132 #endif 133 134 /* Use common timer */ 135 #define CONFIG_SYS_TIMER_COUNTS_DOWN 136 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) 137 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK 138 139 #endif /* _KW_CONFIG_H */ 140