1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2011 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Lei Wen <leiwen@marvell.com> 6 */ 7 8 /* 9 * This file should be included in board config header file. 10 * 11 * It supports common definitions for Kirkwood platform 12 */ 13 14 #ifndef _KW_CONFIG_H 15 #define _KW_CONFIG_H 16 17 #if defined (CONFIG_KW88F6281) 18 #include <asm/arch/kw88f6281.h> 19 #elif defined (CONFIG_KW88F6192) 20 #include <asm/arch/kw88f6192.h> 21 #else 22 #error "SOC Name not defined" 23 #endif /* CONFIG_KW88F6281 */ 24 25 #include <asm/arch/soc.h> 26 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ 27 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ 28 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ 29 30 /* 31 * By default kwbimage.cfg from board specific folder is used 32 * If for some board, different configuration file need to be used, 33 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 34 */ 35 #ifndef CONFIG_SYS_KWD_CONFIG 36 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg 37 #endif /* CONFIG_SYS_KWD_CONFIG */ 38 39 /* Kirkwood has 2k of Security SRAM, use it for SP */ 40 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 41 #define CONFIG_NR_DRAM_BANKS_MAX 2 42 43 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE 44 #define MV_UART_CONSOLE_BASE KW_UART0_BASE 45 #define MV_SATA_BASE KW_SATA_BASE 46 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET 47 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET 48 49 /* 50 * NAND configuration 51 */ 52 #ifdef CONFIG_CMD_NAND 53 #define CONFIG_NAND_KIRKWOOD 54 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ 55 #define NAND_ALLOW_ERASE_ALL 1 56 #endif 57 58 /* 59 * SPI Flash configuration 60 */ 61 #ifdef CONFIG_CMD_SF 62 #ifndef CONFIG_ENV_SPI_BUS 63 # define CONFIG_ENV_SPI_BUS 0 64 #endif 65 #ifndef CONFIG_ENV_SPI_CS 66 # define CONFIG_ENV_SPI_CS 0 67 #endif 68 #ifndef CONFIG_ENV_SPI_MAX_HZ 69 # define CONFIG_ENV_SPI_MAX_HZ 50000000 70 #endif 71 #endif 72 73 /* 74 * Ethernet Driver configuration 75 */ 76 #ifdef CONFIG_CMD_NET 77 #define CONFIG_NETCONSOLE /* include NetConsole support */ 78 #define CONFIG_MII /* expose smi ove miiphy interface */ 79 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 80 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 81 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 82 #endif /* CONFIG_CMD_NET */ 83 84 /* 85 * USB/EHCI 86 */ 87 #ifdef CONFIG_CMD_USB 88 #define CONFIG_EHCI_IS_TDI 89 #endif /* CONFIG_CMD_USB */ 90 91 /* 92 * IDE Support on SATA ports 93 */ 94 #ifdef CONFIG_IDE 95 #define __io 96 #define CONFIG_IDE_PREINIT 97 #define CONFIG_MVSATA_IDE_USE_PORT1 98 /* Needs byte-swapping for ATA data register */ 99 #define CONFIG_IDE_SWAP_IO 100 /* Data, registers and alternate blocks are at the same offset */ 101 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 102 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 103 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 104 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 105 #define CONFIG_SYS_ATA_STRIDE 4 106 /* Controller supports 48-bits LBA addressing */ 107 #define CONFIG_LBA48 108 /* CONFIG_IDE requires some #defines for ATA registers */ 109 #define CONFIG_SYS_IDE_MAXBUS 2 110 #define CONFIG_SYS_IDE_MAXDEVICE 2 111 /* ATA registers base is at SATA controller base */ 112 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE 113 #endif /* CONFIG_IDE */ 114 115 /* 116 * I2C related stuff 117 */ 118 #if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C) 119 #ifndef CONFIG_SYS_I2C_SOFT 120 #define CONFIG_SYS_I2C 121 #define CONFIG_SYS_I2C_MVTWSI 122 #endif 123 #define CONFIG_SYS_I2C_SLAVE 0x0 124 #define CONFIG_SYS_I2C_SPEED 100000 125 #endif 126 127 /* Use common timer */ 128 #define CONFIG_SYS_TIMER_COUNTS_DOWN 129 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) 130 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK 131 132 #endif /* _KW_CONFIG_H */ 133