1 /* 2 * Keystone2: Architecture initialization 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <ns16550.h> 12 #include <asm/io.h> 13 #include <asm/arch/msmc.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/psc_defs.h> 17 18 #define MAX_PCI_PORTS 2 19 enum pci_mode { 20 ENDPOINT, 21 LEGACY_ENDPOINT, 22 ROOTCOMPLEX, 23 }; 24 25 #define DEVCFG_MODE_MASK (BIT(2) | BIT(1)) 26 #define DEVCFG_MODE_SHIFT 1 27 28 void chip_configuration_unlock(void) 29 { 30 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); 31 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); 32 } 33 34 #ifdef CONFIG_SOC_K2L 35 void osr_init(void) 36 { 37 u32 i; 38 u32 j; 39 u32 val; 40 u32 base = KS2_OSR_CFG_BASE; 41 u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS]; 42 43 /* Enable the OSR clock domain */ 44 psc_enable_module(KS2_LPSC_OSR); 45 46 /* Disable OSR ECC check for all the ram banks */ 47 for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) { 48 val = i | KS2_OSR_ECC_VEC_TRIG_RD | 49 (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH); 50 51 writel(val , base + KS2_OSR_ECC_VEC); 52 53 /** 54 * wait till read is done. 55 * Print should be added after earlyprintk support is added. 56 */ 57 for (j = 0; j < 10000; j++) { 58 val = readl(base + KS2_OSR_ECC_VEC); 59 if (val & KS2_OSR_ECC_VEC_RD_DONE) 60 break; 61 } 62 63 ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^ 64 KS2_OSR_ECC_CTRL_CHK; 65 66 writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4); 67 writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL); 68 } 69 70 /* Reset OSR memory to all zeros */ 71 for (i = 0; i < KS2_OSR_SIZE; i += 4) 72 writel(0, KS2_OSR_DATA_BASE + i); 73 74 /* Enable OSR ECC check for all the ram banks */ 75 for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) 76 writel(ecc_ctrl[i] | 77 KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL); 78 } 79 #endif 80 81 /* Function to set up PCIe mode */ 82 static void config_pcie_mode(int pcie_port, enum pci_mode mode) 83 { 84 u32 val = __raw_readl(KS2_DEVCFG); 85 86 if (pcie_port >= MAX_PCI_PORTS) 87 return; 88 89 /** 90 * each pci port has two bits for mode and it starts at 91 * bit 1. So use port number to get the right bit position. 92 */ 93 pcie_port <<= 1; 94 val &= ~(DEVCFG_MODE_MASK << pcie_port); 95 val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port); 96 __raw_writel(val, KS2_DEVCFG); 97 } 98 99 int arch_cpu_init(void) 100 { 101 chip_configuration_unlock(); 102 icache_enable(); 103 104 msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS); 105 msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP); 106 msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP); 107 msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0); 108 109 /* Initialize the PCIe-0 to work as Root Complex */ 110 config_pcie_mode(0, ROOTCOMPLEX); 111 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) 112 msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1); 113 /* Initialize the PCIe-1 to work as Root Complex */ 114 config_pcie_mode(1, ROOTCOMPLEX); 115 #endif 116 #ifdef CONFIG_SOC_K2L 117 osr_init(); 118 #endif 119 120 /* 121 * just initialise the COM2 port so that TI specific 122 * UART register PWREMU_MGMT is initialized. Linux UART 123 * driver doesn't handle this. 124 */ 125 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2), 126 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); 127 128 return 0; 129 } 130 131 void reset_cpu(ulong addr) 132 { 133 volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL); 134 u32 tmp; 135 136 tmp = *rstctrl & KS2_RSTCTRL_MASK; 137 *rstctrl = tmp | KS2_RSTCTRL_KEY; 138 139 *rstctrl &= KS2_RSTCTRL_SWRST; 140 141 for (;;) 142 ; 143 } 144 145 void enable_caches(void) 146 { 147 #ifndef CONFIG_SYS_DCACHE_OFF 148 /* Enable D-cache. I-cache is already enabled in start.S */ 149 dcache_enable(); 150 #endif 151 } 152