1 /*
2  * (C) Copyright 2012-2014
3  *     Texas Instruments Incorporated, <www.ti.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7 #ifndef _PSC_DEFS_H_
8 #define _PSC_DEFS_H_
9 
10 #include <asm/arch/hardware.h>
11 
12 /*
13  * FILE PURPOSE: Local Power Sleep Controller definitions
14  *
15  * FILE NAME: psc_defs.h
16  *
17  * DESCRIPTION: Provides local definitions for the power saver controller
18  *
19  */
20 
21 /* Register offsets */
22 #define PSC_REG_PTCMD           0x120
23 #define PSC_REG_PSTAT	        0x128
24 #define PSC_REG_PDSTAT(x)       (0x200 + (4 * (x)))
25 #define PSC_REG_PDCTL(x)        (0x300 + (4 * (x)))
26 #define PSC_REG_MDCFG(x)        (0x600 + (4 * (x)))
27 #define PSC_REG_MDSTAT(x)       (0x800 + (4 * (x)))
28 #define PSC_REG_MDCTL(x)        (0xa00 + (4 * (x)))
29 
30 
31 static inline u32 _boot_bit_mask(u32 x, u32 y)
32 {
33 	u32 val = (1 << (x - y + 1)) - 1;
34 	return val << y;
35 }
36 
37 static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y)
38 {
39 	u32 val = z & _boot_bit_mask(x, y);
40 	return val >> y;
41 }
42 
43 static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y)
44 {
45 	u32 mask = _boot_bit_mask(x, y);
46 
47 	return (z & ~mask) | ((f << y) & mask);
48 }
49 
50 /* PDCTL */
51 #define PSC_REG_PDCTL_SET_NEXT(x, y)        boot_set_bitfield((x), (y), 0, 0)
52 #define PSC_REG_PDCTL_SET_PDMODE(x, y)      boot_set_bitfield((x), (y), 15, 12)
53 
54 /* PDSTAT */
55 #define PSC_REG_PDSTAT_GET_STATE(x)         boot_read_bitfield((x), 4, 0)
56 
57 /* MDCFG */
58 #define PSC_REG_MDCFG_GET_PD(x)             boot_read_bitfield((x), 20, 16)
59 #define PSC_REG_MDCFG_GET_RESET_ISO(x)      boot_read_bitfield((x), 14, 14)
60 
61 /* MDCTL */
62 #define PSC_REG_MDCTL_SET_NEXT(x, y)        boot_set_bitfield((x), (y), 4, 0)
63 #define PSC_REG_MDCTL_SET_LRSTZ(x, y)       boot_set_bitfield((x), (y), 8, 8)
64 #define PSC_REG_MDCTL_GET_LRSTZ(x)          boot_read_bitfield((x), 8, 8)
65 #define PSC_REG_MDCTL_SET_RESET_ISO(x, y)   boot_set_bitfield((x), (y), \
66 								  12, 12)
67 
68 /* MDSTAT */
69 #define PSC_REG_MDSTAT_GET_STATUS(x)        boot_read_bitfield((x), 5, 0)
70 #define PSC_REG_MDSTAT_GET_LRSTZ(x)         boot_read_bitfield((x), 8, 8)
71 #define PSC_REG_MDSTAT_GET_LRSTDONE(x)      boot_read_bitfield((x), 9, 9)
72 #define PSC_REG_MDSTAT_GET_MRSTZ(x)         boot_read_bitfield((x), 10, 10)
73 #define PSC_REG_MDSTAT_GET_MRSTDONE(x)      boot_read_bitfield((x), 11, 11)
74 
75 /* PDCTL states */
76 #define PSC_REG_VAL_PDCTL_NEXT_ON           1
77 #define PSC_REG_VAL_PDCTL_NEXT_OFF          0
78 
79 #define PSC_REG_VAL_PDCTL_PDMODE_SLEEP      0
80 
81 /* MDCTL states */
82 #define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE     0
83 #define PSC_REG_VAL_MDCTL_NEXT_OFF              2
84 #define PSC_REG_VAL_MDCTL_NEXT_ON               3
85 
86 /* MDSTAT states */
87 #define PSC_REG_VAL_MDSTAT_STATE_ON             3
88 #define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
89 #define PSC_REG_VAL_MDSTAT_STATE_OFF            2
90 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1       0x20
91 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2       0x21
92 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3       0x22
93 
94 /*
95  * Timeout limit on checking PTSTAT. This is the number of times the
96  * wait function will be called before giving up.
97  */
98 #define PSC_PTSTAT_TIMEOUT_LIMIT    100
99 
100 u32 psc_get_domain_num(u32 mod_num);
101 int psc_enable_module(u32 mod_num);
102 int psc_disable_module(u32 mod_num);
103 int psc_disable_domain(u32 domain_num);
104 int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks);
105 int psc_module_release_from_reset(u32 mod_num);
106 
107 #endif /* _PSC_DEFS_H_ */
108