1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2012-2014
4  *     Texas Instruments Incorporated, <www.ti.com>
5  */
6 #ifndef _PSC_DEFS_H_
7 #define _PSC_DEFS_H_
8 
9 #include <asm/arch/hardware.h>
10 
11 /*
12  * FILE PURPOSE: Local Power Sleep Controller definitions
13  *
14  * FILE NAME: psc_defs.h
15  *
16  * DESCRIPTION: Provides local definitions for the power saver controller
17  *
18  */
19 
20 /* Register offsets */
21 #define PSC_REG_PTCMD           0x120
22 #define PSC_REG_PSTAT	        0x128
23 #define PSC_REG_PDSTAT(x)       (0x200 + (4 * (x)))
24 #define PSC_REG_PDCTL(x)        (0x300 + (4 * (x)))
25 #define PSC_REG_MDCFG(x)        (0x600 + (4 * (x)))
26 #define PSC_REG_MDSTAT(x)       (0x800 + (4 * (x)))
27 #define PSC_REG_MDCTL(x)        (0xa00 + (4 * (x)))
28 
29 
30 static inline u32 _boot_bit_mask(u32 x, u32 y)
31 {
32 	u32 val = (1 << (x - y + 1)) - 1;
33 	return val << y;
34 }
35 
36 static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y)
37 {
38 	u32 val = z & _boot_bit_mask(x, y);
39 	return val >> y;
40 }
41 
42 static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y)
43 {
44 	u32 mask = _boot_bit_mask(x, y);
45 
46 	return (z & ~mask) | ((f << y) & mask);
47 }
48 
49 /* PDCTL */
50 #define PSC_REG_PDCTL_SET_NEXT(x, y)        boot_set_bitfield((x), (y), 0, 0)
51 #define PSC_REG_PDCTL_SET_PDMODE(x, y)      boot_set_bitfield((x), (y), 15, 12)
52 
53 /* PDSTAT */
54 #define PSC_REG_PDSTAT_GET_STATE(x)         boot_read_bitfield((x), 4, 0)
55 
56 /* MDCFG */
57 #define PSC_REG_MDCFG_GET_PD(x)             boot_read_bitfield((x), 20, 16)
58 #define PSC_REG_MDCFG_GET_RESET_ISO(x)      boot_read_bitfield((x), 14, 14)
59 
60 /* MDCTL */
61 #define PSC_REG_MDCTL_SET_NEXT(x, y)        boot_set_bitfield((x), (y), 4, 0)
62 #define PSC_REG_MDCTL_SET_LRSTZ(x, y)       boot_set_bitfield((x), (y), 8, 8)
63 #define PSC_REG_MDCTL_GET_LRSTZ(x)          boot_read_bitfield((x), 8, 8)
64 #define PSC_REG_MDCTL_SET_RESET_ISO(x, y)   boot_set_bitfield((x), (y), \
65 								  12, 12)
66 
67 /* MDSTAT */
68 #define PSC_REG_MDSTAT_GET_STATUS(x)        boot_read_bitfield((x), 5, 0)
69 #define PSC_REG_MDSTAT_GET_LRSTZ(x)         boot_read_bitfield((x), 8, 8)
70 #define PSC_REG_MDSTAT_GET_LRSTDONE(x)      boot_read_bitfield((x), 9, 9)
71 #define PSC_REG_MDSTAT_GET_MRSTZ(x)         boot_read_bitfield((x), 10, 10)
72 #define PSC_REG_MDSTAT_GET_MRSTDONE(x)      boot_read_bitfield((x), 11, 11)
73 
74 /* PDCTL states */
75 #define PSC_REG_VAL_PDCTL_NEXT_ON           1
76 #define PSC_REG_VAL_PDCTL_NEXT_OFF          0
77 
78 #define PSC_REG_VAL_PDCTL_PDMODE_SLEEP      0
79 
80 /* MDCTL states */
81 #define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE     0
82 #define PSC_REG_VAL_MDCTL_NEXT_OFF              2
83 #define PSC_REG_VAL_MDCTL_NEXT_ON               3
84 
85 /* MDSTAT states */
86 #define PSC_REG_VAL_MDSTAT_STATE_ON             3
87 #define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
88 #define PSC_REG_VAL_MDSTAT_STATE_OFF            2
89 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1       0x20
90 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2       0x21
91 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3       0x22
92 
93 /*
94  * Timeout limit on checking PTSTAT. This is the number of times the
95  * wait function will be called before giving up.
96  */
97 #define PSC_PTSTAT_TIMEOUT_LIMIT    100
98 
99 u32 psc_get_domain_num(u32 mod_num);
100 int psc_enable_module(u32 mod_num);
101 int psc_disable_module(u32 mod_num);
102 int psc_disable_domain(u32 domain_num);
103 int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks);
104 int psc_module_release_from_reset(u32 mod_num);
105 
106 #endif /* _PSC_DEFS_H_ */
107