1 /*
2  * (C) Copyright 2012-2014
3  *     Texas Instruments Incorporated, <www.ti.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7 #ifndef _PSC_DEFS_H_
8 #define _PSC_DEFS_H_
9 
10 #include <asm/arch/hardware.h>
11 
12 /*
13  * FILE PURPOSE: Local Power Sleep Controller definitions
14  *
15  * FILE NAME: psc_defs.h
16  *
17  * DESCRIPTION: Provides local definitions for the power saver controller
18  *
19  */
20 
21 /* Register offsets */
22 #define PSC_REG_PTCMD           0x120
23 #define PSC_REG_PSTAT	        0x128
24 #define PSC_REG_PDSTAT(x)       (0x200 + (4 * (x)))
25 #define PSC_REG_PDCTL(x)        (0x300 + (4 * (x)))
26 #define PSC_REG_MDCFG(x)        (0x600 + (4 * (x)))
27 #define PSC_REG_MDSTAT(x)       (0x800 + (4 * (x)))
28 #define PSC_REG_MDCTL(x)        (0xa00 + (4 * (x)))
29 
30 #define BOOTBITMASK(x, y)     ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
31 				  (u32)1)) << ((u32)y)))
32 
33 #define BOOT_READ_BITFIELD(z, x, y)    ((((u32)z) & BOOTBITMASK(x, y)) >> (y))
34 #define BOOT_SET_BITFIELD(z, f, x, y)  ((((u32)z) & ~BOOTBITMASK(x, y)) | \
35 					((((u32)f) << (y)) & BOOTBITMASK(x, y)))
36 
37 /* PDCTL */
38 #define PSC_REG_PDCTL_SET_NEXT(x, y)        BOOT_SET_BITFIELD((x), (y), 0, 0)
39 #define PSC_REG_PDCTL_SET_PDMODE(x, y)      BOOT_SET_BITFIELD((x), (y), 15, 12)
40 
41 /* PDSTAT */
42 #define PSC_REG_PDSTAT_GET_STATE(x)         BOOT_READ_BITFIELD((x), 4, 0)
43 
44 /* MDCFG */
45 #define PSC_REG_MDCFG_GET_PD(x)             BOOT_READ_BITFIELD((x), 20, 16)
46 #define PSC_REG_MDCFG_GET_RESET_ISO(x)      BOOT_READ_BITFIELD((x), 14, 14)
47 
48 /* MDCTL */
49 #define PSC_REG_MDCTL_SET_NEXT(x, y)        BOOT_SET_BITFIELD((x), (y), 4, 0)
50 #define PSC_REG_MDCTL_SET_LRSTZ(x, y)       BOOT_SET_BITFIELD((x), (y), 8, 8)
51 #define PSC_REG_MDCTL_GET_LRSTZ(x)          BOOT_READ_BITFIELD((x), 8, 8)
52 #define PSC_REG_MDCTL_SET_RESET_ISO(x, y)   BOOT_SET_BITFIELD((x), (y), \
53 								  12, 12)
54 
55 /* MDSTAT */
56 #define PSC_REG_MDSTAT_GET_STATUS(x)        BOOT_READ_BITFIELD((x), 5, 0)
57 #define PSC_REG_MDSTAT_GET_LRSTZ(x)         BOOT_READ_BITFIELD((x), 8, 8)
58 #define PSC_REG_MDSTAT_GET_LRSTDONE(x)      BOOT_READ_BITFIELD((x), 9, 9)
59 #define PSC_REG_MDSTAT_GET_MRSTZ(x)         BOOT_READ_BITFIELD((x), 10, 10)
60 #define PSC_REG_MDSTAT_GET_MRSTDONE(x)      BOOT_READ_BITFIELD((x), 11, 11)
61 
62 /* PDCTL states */
63 #define PSC_REG_VAL_PDCTL_NEXT_ON           1
64 #define PSC_REG_VAL_PDCTL_NEXT_OFF          0
65 
66 #define PSC_REG_VAL_PDCTL_PDMODE_SLEEP      0
67 
68 /* MDCTL states */
69 #define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE     0
70 #define PSC_REG_VAL_MDCTL_NEXT_OFF              2
71 #define PSC_REG_VAL_MDCTL_NEXT_ON               3
72 
73 /* MDSTAT states */
74 #define PSC_REG_VAL_MDSTAT_STATE_ON             3
75 #define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
76 #define PSC_REG_VAL_MDSTAT_STATE_OFF            2
77 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1       0x20
78 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2       0x21
79 #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3       0x22
80 
81 /*
82  * Timeout limit on checking PTSTAT. This is the number of times the
83  * wait function will be called before giving up.
84  */
85 #define PSC_PTSTAT_TIMEOUT_LIMIT    100
86 
87 u32 psc_get_domain_num(u32 mod_num);
88 int psc_enable_module(u32 mod_num);
89 int psc_disable_module(u32 mod_num);
90 int psc_disable_domain(u32 domain_num);
91 int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks);
92 int psc_module_release_from_reset(u32 mod_num);
93 
94 #endif /* _PSC_DEFS_H_ */
95