1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 25dd6af2eSVitaly Andrianov /* 35dd6af2eSVitaly Andrianov * K2G: Pinmux configuration 45dd6af2eSVitaly Andrianov * 55dd6af2eSVitaly Andrianov * (C) Copyright 2015 65dd6af2eSVitaly Andrianov * Texas Instruments Incorporated, <www.ti.com> 75dd6af2eSVitaly Andrianov */ 85dd6af2eSVitaly Andrianov 95dd6af2eSVitaly Andrianov #ifndef __ASM_ARCH_MUX_K2G_H 105dd6af2eSVitaly Andrianov #define __ASM_ARCH_MUX_K2G_H 115dd6af2eSVitaly Andrianov 125dd6af2eSVitaly Andrianov #include <common.h> 135dd6af2eSVitaly Andrianov #include <asm/io.h> 145dd6af2eSVitaly Andrianov 155dd6af2eSVitaly Andrianov #define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000) 165dd6af2eSVitaly Andrianov 175dd6af2eSVitaly Andrianov /* 185dd6af2eSVitaly Andrianov * 20:19 - buffer class RW fixed 195dd6af2eSVitaly Andrianov * 18 - rxactive (Input enabled for the pad ) 0 - Di; 1 - En; 205dd6af2eSVitaly Andrianov * 17 - pulltypesel (0 - PULLDOWN; 1 - PULLUP); 215dd6af2eSVitaly Andrianov * 16 - pulluden (0 - PULLUP/DOWN EN; 1 - DI); 225dd6af2eSVitaly Andrianov * 3:0 - muxmode (available modes 0:5) 235dd6af2eSVitaly Andrianov */ 245dd6af2eSVitaly Andrianov 255dd6af2eSVitaly Andrianov #define PIN_IEN (1 << 18) /* pin input enabled */ 265dd6af2eSVitaly Andrianov #define PIN_PDIS (1 << 16) /* pull up/down disabled */ 275dd6af2eSVitaly Andrianov #define PIN_PTU (1 << 17) /* pull up */ 285dd6af2eSVitaly Andrianov #define PIN_PTD (0 << 17) /* pull down */ 295dd6af2eSVitaly Andrianov 305dd6af2eSVitaly Andrianov #define MODE(m) ((m) & 0x7) 315dd6af2eSVitaly Andrianov #define MAX_PIN_N 260 325dd6af2eSVitaly Andrianov 335dd6af2eSVitaly Andrianov #define MUX_CFG(value, index) \ 345dd6af2eSVitaly Andrianov __raw_writel(\ 355dd6af2eSVitaly Andrianov (value) | \ 365dd6af2eSVitaly Andrianov (__raw_readl(K2G_PADCFG_REG + (index << 2)) & \ 375dd6af2eSVitaly Andrianov (0x3 << 19)),\ 385dd6af2eSVitaly Andrianov (K2G_PADCFG_REG + (index << 2))\ 395dd6af2eSVitaly Andrianov ); 405dd6af2eSVitaly Andrianov 415dd6af2eSVitaly Andrianov struct pin_cfg { 425dd6af2eSVitaly Andrianov int reg_inx; 435dd6af2eSVitaly Andrianov u32 val; 445dd6af2eSVitaly Andrianov }; 455dd6af2eSVitaly Andrianov 465dd6af2eSVitaly Andrianov static inline void configure_pin_mux(struct pin_cfg *pin_mux) 475dd6af2eSVitaly Andrianov { 485dd6af2eSVitaly Andrianov if (!pin_mux) 495dd6af2eSVitaly Andrianov return; 505dd6af2eSVitaly Andrianov 515dd6af2eSVitaly Andrianov while ((pin_mux->reg_inx >= 0) && (pin_mux->reg_inx < MAX_PIN_N)) { 525dd6af2eSVitaly Andrianov MUX_CFG(pin_mux->val, pin_mux->reg_inx); 535dd6af2eSVitaly Andrianov pin_mux++; 545dd6af2eSVitaly Andrianov } 555dd6af2eSVitaly Andrianov } 565dd6af2eSVitaly Andrianov 575dd6af2eSVitaly Andrianov #endif /* __ASM_ARCH_MUX_K2G_H */ 58