1*5dd6af2eSVitaly Andrianov /* 2*5dd6af2eSVitaly Andrianov * K2G: Pinmux configuration 3*5dd6af2eSVitaly Andrianov * 4*5dd6af2eSVitaly Andrianov * (C) Copyright 2015 5*5dd6af2eSVitaly Andrianov * Texas Instruments Incorporated, <www.ti.com> 6*5dd6af2eSVitaly Andrianov * 7*5dd6af2eSVitaly Andrianov * SPDX-License-Identifier: GPL-2.0+ 8*5dd6af2eSVitaly Andrianov */ 9*5dd6af2eSVitaly Andrianov 10*5dd6af2eSVitaly Andrianov #ifndef __ASM_ARCH_MUX_K2G_H 11*5dd6af2eSVitaly Andrianov #define __ASM_ARCH_MUX_K2G_H 12*5dd6af2eSVitaly Andrianov 13*5dd6af2eSVitaly Andrianov #include <common.h> 14*5dd6af2eSVitaly Andrianov #include <asm/io.h> 15*5dd6af2eSVitaly Andrianov 16*5dd6af2eSVitaly Andrianov #define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000) 17*5dd6af2eSVitaly Andrianov 18*5dd6af2eSVitaly Andrianov /* 19*5dd6af2eSVitaly Andrianov * 20:19 - buffer class RW fixed 20*5dd6af2eSVitaly Andrianov * 18 - rxactive (Input enabled for the pad ) 0 - Di; 1 - En; 21*5dd6af2eSVitaly Andrianov * 17 - pulltypesel (0 - PULLDOWN; 1 - PULLUP); 22*5dd6af2eSVitaly Andrianov * 16 - pulluden (0 - PULLUP/DOWN EN; 1 - DI); 23*5dd6af2eSVitaly Andrianov * 3:0 - muxmode (available modes 0:5) 24*5dd6af2eSVitaly Andrianov */ 25*5dd6af2eSVitaly Andrianov 26*5dd6af2eSVitaly Andrianov #define PIN_IEN (1 << 18) /* pin input enabled */ 27*5dd6af2eSVitaly Andrianov #define PIN_PDIS (1 << 16) /* pull up/down disabled */ 28*5dd6af2eSVitaly Andrianov #define PIN_PTU (1 << 17) /* pull up */ 29*5dd6af2eSVitaly Andrianov #define PIN_PTD (0 << 17) /* pull down */ 30*5dd6af2eSVitaly Andrianov 31*5dd6af2eSVitaly Andrianov #define MODE(m) ((m) & 0x7) 32*5dd6af2eSVitaly Andrianov #define MAX_PIN_N 260 33*5dd6af2eSVitaly Andrianov 34*5dd6af2eSVitaly Andrianov #define MUX_CFG(value, index) \ 35*5dd6af2eSVitaly Andrianov __raw_writel(\ 36*5dd6af2eSVitaly Andrianov (value) | \ 37*5dd6af2eSVitaly Andrianov (__raw_readl(K2G_PADCFG_REG + (index << 2)) & \ 38*5dd6af2eSVitaly Andrianov (0x3 << 19)),\ 39*5dd6af2eSVitaly Andrianov (K2G_PADCFG_REG + (index << 2))\ 40*5dd6af2eSVitaly Andrianov ); 41*5dd6af2eSVitaly Andrianov 42*5dd6af2eSVitaly Andrianov struct pin_cfg { 43*5dd6af2eSVitaly Andrianov int reg_inx; 44*5dd6af2eSVitaly Andrianov u32 val; 45*5dd6af2eSVitaly Andrianov }; 46*5dd6af2eSVitaly Andrianov 47*5dd6af2eSVitaly Andrianov static inline void configure_pin_mux(struct pin_cfg *pin_mux) 48*5dd6af2eSVitaly Andrianov { 49*5dd6af2eSVitaly Andrianov if (!pin_mux) 50*5dd6af2eSVitaly Andrianov return; 51*5dd6af2eSVitaly Andrianov 52*5dd6af2eSVitaly Andrianov while ((pin_mux->reg_inx >= 0) && (pin_mux->reg_inx < MAX_PIN_N)) { 53*5dd6af2eSVitaly Andrianov MUX_CFG(pin_mux->val, pin_mux->reg_inx); 54*5dd6af2eSVitaly Andrianov pin_mux++; 55*5dd6af2eSVitaly Andrianov } 56*5dd6af2eSVitaly Andrianov } 57*5dd6af2eSVitaly Andrianov 58*5dd6af2eSVitaly Andrianov #endif /* __ASM_ARCH_MUX_K2G_H */ 59