1 /* 2 * K2HK: SoC definitions 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ASM_ARCH_HARDWARE_K2HK_H 11 #define __ASM_ARCH_HARDWARE_K2HK_H 12 13 #define KS2_ARM_PLL_EN BIT(13) 14 15 /* PA SS Registers */ 16 #define KS2_PASS_BASE 0x02000000 17 18 /* Power and Sleep Controller (PSC) Domains */ 19 #define KS2_LPSC_MOD 0 20 #define KS2_LPSC_DUMMY1 1 21 #define KS2_LPSC_USB 2 22 #define KS2_LPSC_EMIF25_SPI 3 23 #define KS2_LPSC_TSIP 4 24 #define KS2_LPSC_DEBUGSS_TRC 5 25 #define KS2_LPSC_TETB_TRC 6 26 #define KS2_LPSC_PKTPROC 7 27 #define KS2_LPSC_PA KS2_LPSC_PKTPROC 28 #define KS2_LPSC_SGMII 8 29 #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 30 #define KS2_LPSC_CRYPTO 9 31 #define KS2_LPSC_PCIE 10 32 #define KS2_LPSC_SRIO 11 33 #define KS2_LPSC_VUSR0 12 34 #define KS2_LPSC_CHIP_SRSS 13 35 #define KS2_LPSC_MSMC 14 36 #define KS2_LPSC_GEM_1 16 37 #define KS2_LPSC_GEM_2 17 38 #define KS2_LPSC_GEM_3 18 39 #define KS2_LPSC_GEM_4 19 40 #define KS2_LPSC_GEM_5 20 41 #define KS2_LPSC_GEM_6 21 42 #define KS2_LPSC_GEM_7 22 43 #define KS2_LPSC_EMIF4F_DDR3A 23 44 #define KS2_LPSC_EMIF4F_DDR3B 24 45 #define KS2_LPSC_TAC 25 46 #define KS2_LPSC_RAC 26 47 #define KS2_LPSC_RAC_1 27 48 #define KS2_LPSC_FFTC_A 28 49 #define KS2_LPSC_FFTC_B 29 50 #define KS2_LPSC_FFTC_C 30 51 #define KS2_LPSC_FFTC_D 31 52 #define KS2_LPSC_FFTC_E 32 53 #define KS2_LPSC_FFTC_F 33 54 #define KS2_LPSC_AI2 34 55 #define KS2_LPSC_TCP3D_0 35 56 #define KS2_LPSC_TCP3D_1 36 57 #define KS2_LPSC_TCP3D_2 37 58 #define KS2_LPSC_TCP3D_3 38 59 #define KS2_LPSC_VCP2X4_A 39 60 #define KS2_LPSC_CP2X4_B 40 61 #define KS2_LPSC_VCP2X4_C 41 62 #define KS2_LPSC_VCP2X4_D 42 63 #define KS2_LPSC_VCP2X4_E 43 64 #define KS2_LPSC_VCP2X4_F 44 65 #define KS2_LPSC_VCP2X4_G 45 66 #define KS2_LPSC_VCP2X4_H 46 67 #define KS2_LPSC_BCP 47 68 #define KS2_LPSC_DXB 48 69 #define KS2_LPSC_VUSR1 49 70 #define KS2_LPSC_XGE 50 71 #define KS2_LPSC_ARM_SREFLEX 51 72 73 /* DDR3B definitions */ 74 #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 75 #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 76 #define KS2_DDR3B_DDRPHYC 0x02328000 77 78 #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ 79 #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 80 channel 29 */ 81 82 /* SGMII SerDes */ 83 #define KS2_LANES_PER_SGMII_SERDES 4 84 85 /* Number of DSP cores */ 86 #define KS2_NUM_DSPS 8 87 88 /* NETCP pktdma */ 89 #define KS2_NETCP_PDMA_CTRL_BASE 0x02004000 90 #define KS2_NETCP_PDMA_TX_BASE 0x02004400 91 #define KS2_NETCP_PDMA_TX_CH_NUM 9 92 #define KS2_NETCP_PDMA_RX_BASE 0x02004800 93 #define KS2_NETCP_PDMA_RX_CH_NUM 26 94 #define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 95 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 96 #define KS2_NETCP_PDMA_RX_FLOW_NUM 32 97 #define KS2_NETCP_PDMA_TX_SND_QUEUE 648 98 99 /* NETCP */ 100 #define KS2_NETCP_BASE 0x02000000 101 102 #endif /* __ASM_ARCH_HARDWARE_H */ 103