1*dc7de222SMasahiro Yamada /* 2*dc7de222SMasahiro Yamada * K2HK: SoC definitions 3*dc7de222SMasahiro Yamada * 4*dc7de222SMasahiro Yamada * (C) Copyright 2012-2014 5*dc7de222SMasahiro Yamada * Texas Instruments Incorporated, <www.ti.com> 6*dc7de222SMasahiro Yamada * 7*dc7de222SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 8*dc7de222SMasahiro Yamada */ 9*dc7de222SMasahiro Yamada 10*dc7de222SMasahiro Yamada #ifndef __ASM_ARCH_HARDWARE_K2HK_H 11*dc7de222SMasahiro Yamada #define __ASM_ARCH_HARDWARE_K2HK_H 12*dc7de222SMasahiro Yamada 13*dc7de222SMasahiro Yamada #define KS2_ARM_PLL_EN BIT(13) 14*dc7de222SMasahiro Yamada 15*dc7de222SMasahiro Yamada /* PA SS Registers */ 16*dc7de222SMasahiro Yamada #define KS2_PASS_BASE 0x02000000 17*dc7de222SMasahiro Yamada 18*dc7de222SMasahiro Yamada /* PLL control registers */ 19*dc7de222SMasahiro Yamada #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) 20*dc7de222SMasahiro Yamada #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) 21*dc7de222SMasahiro Yamada 22*dc7de222SMasahiro Yamada /* Power and Sleep Controller (PSC) Domains */ 23*dc7de222SMasahiro Yamada #define KS2_LPSC_MOD 0 24*dc7de222SMasahiro Yamada #define KS2_LPSC_DUMMY1 1 25*dc7de222SMasahiro Yamada #define KS2_LPSC_USB 2 26*dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF25_SPI 3 27*dc7de222SMasahiro Yamada #define KS2_LPSC_TSIP 4 28*dc7de222SMasahiro Yamada #define KS2_LPSC_DEBUGSS_TRC 5 29*dc7de222SMasahiro Yamada #define KS2_LPSC_TETB_TRC 6 30*dc7de222SMasahiro Yamada #define KS2_LPSC_PKTPROC 7 31*dc7de222SMasahiro Yamada #define KS2_LPSC_PA KS2_LPSC_PKTPROC 32*dc7de222SMasahiro Yamada #define KS2_LPSC_SGMII 8 33*dc7de222SMasahiro Yamada #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 34*dc7de222SMasahiro Yamada #define KS2_LPSC_CRYPTO 9 35*dc7de222SMasahiro Yamada #define KS2_LPSC_PCIE 10 36*dc7de222SMasahiro Yamada #define KS2_LPSC_SRIO 11 37*dc7de222SMasahiro Yamada #define KS2_LPSC_VUSR0 12 38*dc7de222SMasahiro Yamada #define KS2_LPSC_CHIP_SRSS 13 39*dc7de222SMasahiro Yamada #define KS2_LPSC_MSMC 14 40*dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_1 16 41*dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_2 17 42*dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_3 18 43*dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_4 19 44*dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_5 20 45*dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_6 21 46*dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_7 22 47*dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF4F_DDR3A 23 48*dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF4F_DDR3B 24 49*dc7de222SMasahiro Yamada #define KS2_LPSC_TAC 25 50*dc7de222SMasahiro Yamada #define KS2_LPSC_RAC 26 51*dc7de222SMasahiro Yamada #define KS2_LPSC_RAC_1 27 52*dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_A 28 53*dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_B 29 54*dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_C 30 55*dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_D 31 56*dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_E 32 57*dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_F 33 58*dc7de222SMasahiro Yamada #define KS2_LPSC_AI2 34 59*dc7de222SMasahiro Yamada #define KS2_LPSC_TCP3D_0 35 60*dc7de222SMasahiro Yamada #define KS2_LPSC_TCP3D_1 36 61*dc7de222SMasahiro Yamada #define KS2_LPSC_TCP3D_2 37 62*dc7de222SMasahiro Yamada #define KS2_LPSC_TCP3D_3 38 63*dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_A 39 64*dc7de222SMasahiro Yamada #define KS2_LPSC_CP2X4_B 40 65*dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_C 41 66*dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_D 42 67*dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_E 43 68*dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_F 44 69*dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_G 45 70*dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_H 46 71*dc7de222SMasahiro Yamada #define KS2_LPSC_BCP 47 72*dc7de222SMasahiro Yamada #define KS2_LPSC_DXB 48 73*dc7de222SMasahiro Yamada #define KS2_LPSC_VUSR1 49 74*dc7de222SMasahiro Yamada #define KS2_LPSC_XGE 50 75*dc7de222SMasahiro Yamada #define KS2_LPSC_ARM_SREFLEX 51 76*dc7de222SMasahiro Yamada 77*dc7de222SMasahiro Yamada /* DDR3B definitions */ 78*dc7de222SMasahiro Yamada #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 79*dc7de222SMasahiro Yamada #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 80*dc7de222SMasahiro Yamada #define KS2_DDR3B_DDRPHYC 0x02328000 81*dc7de222SMasahiro Yamada 82*dc7de222SMasahiro Yamada #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ 83*dc7de222SMasahiro Yamada #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 84*dc7de222SMasahiro Yamada channel 29 */ 85*dc7de222SMasahiro Yamada 86*dc7de222SMasahiro Yamada /* SGMII SerDes */ 87*dc7de222SMasahiro Yamada #define KS2_LANES_PER_SGMII_SERDES 4 88*dc7de222SMasahiro Yamada 89*dc7de222SMasahiro Yamada /* Number of DSP cores */ 90*dc7de222SMasahiro Yamada #define KS2_NUM_DSPS 8 91*dc7de222SMasahiro Yamada 92*dc7de222SMasahiro Yamada /* NETCP pktdma */ 93*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_CTRL_BASE 0x02004000 94*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_BASE 0x02004400 95*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_CH_NUM 9 96*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_BASE 0x02004800 97*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_CH_NUM 26 98*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 99*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 100*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_FLOW_NUM 32 101*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_SND_QUEUE 648 102*dc7de222SMasahiro Yamada 103*dc7de222SMasahiro Yamada /* NETCP */ 104*dc7de222SMasahiro Yamada #define KS2_NETCP_BASE 0x02000000 105*dc7de222SMasahiro Yamada 106*dc7de222SMasahiro Yamada #endif /* __ASM_ARCH_HARDWARE_H */ 107