1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * K2G: SoC definitions
4  *
5  * (C) Copyright 2015
6  *     Texas Instruments Incorporated, <www.ti.com>
7  */
8 
9 #ifndef __ASM_ARCH_HARDWARE_K2G_H
10 #define __ASM_ARCH_HARDWARE_K2G_H
11 
12 #define KS2_NUM_DSPS			1
13 
14 /* Power and Sleep Controller (PSC) Domains */
15 #define KS2_LPSC_ALWAYSON		0
16 #define KS2_LPSC_PMMC			1
17 #define KS2_LPSC_DEBUG			2
18 #define KS2_LPSC_NSS			3
19 #define KS2_LPSC_SA			4
20 #define KS2_LPSC_TERANET		5
21 #define KS2_LPSC_SYS_COMP		6
22 #define KS2_LPSC_QSPI			7
23 #define KS2_LPSC_MMC			8
24 #define KS2_LPSC_GPMC			9
25 #define KS2_LPSC_MLB			11
26 #define KS2_LPSC_EHRPWM			12
27 #define KS2_LPSC_EQEP			13
28 #define KS2_LPSC_ECAP			14
29 #define KS2_LPSC_MCASP			15
30 #define KS2_LPSC_SR			16
31 #define KS2_LPSC_MSMC			17
32 #ifdef KS2_LPSC_GEM_0
33 #undef KS2_LPSC_GEM_0
34 #endif
35 #define KS2_LPSC_GEM_0			18
36 #define KS2_LPSC_ARM			19
37 #define KS2_LPSC_ASRC			20
38 #define KS2_LPSC_ICSS			21
39 #define KS2_LPSC_DSS			23
40 #define KS2_LPSC_PCIE			24
41 #define KS2_LPSC_USB_0			25
42 #define KS2_LPSC_USB			KS2_LPSC_USB_0
43 #define KS2_LPSC_USB_1			26
44 #define KS2_LPSC_DDR3			27
45 #define KS2_LPSC_SPARE0_LPSC0		28
46 #define KS2_LPSC_SPARE0_LPSC1		29
47 #define KS2_LPSC_SPARE1_LPSC0		30
48 #define KS2_LPSC_SPARE1_LPSC1		31
49 
50 #define KS2_LPSC_CPGMAC			KS2_LPSC_NSS
51 #define KS2_LPSC_CRYPTO			KS2_LPSC_SA
52 
53 /* SGMII SerDes */
54 #define KS2_LANES_PER_SGMII_SERDES	4
55 
56 /* NETCP pktdma */
57 #define KS2_NETCP_PDMA_CTRL_BASE	0x04010000
58 #define KS2_NETCP_PDMA_TX_BASE		0x04011000
59 #define KS2_NETCP_PDMA_TX_CH_NUM	21
60 #define KS2_NETCP_PDMA_RX_BASE		0x04012000
61 #define KS2_NETCP_PDMA_RX_CH_NUM	32
62 #define KS2_NETCP_PDMA_SCHED_BASE	0x04010100
63 #define KS2_NETCP_PDMA_RX_FLOW_BASE	0x04013000
64 #define KS2_NETCP_PDMA_RX_FLOW_NUM	32
65 #define KS2_NETCP_PDMA_TX_SND_QUEUE	5
66 
67 /* NETCP */
68 #define KS2_NETCP_BASE			0x04000000
69 
70 #define K2G_GPIO0_BASE			0X02603000
71 #define K2G_GPIO1_BASE			0X0260a000
72 #define K2G_GPIO1_BANK2_BASE		K2G_GPIO1_BASE + 0x38
73 #define K2G_GPIO_DIR_OFFSET		0x0
74 #define K2G_GPIO_SETDATA_OFFSET		0x8
75 
76 /* BOOTCFG RESETMUX8 */
77 #define KS2_RSTMUX8			(KS2_DEVICE_STATE_CTRL_BASE + 0x328)
78 
79 /* RESETMUX register definitions */
80 #define RSTMUX_LOCK8_SHIFT		0x0
81 #define RSTMUX_LOCK8_MASK		(0x1 << 0)
82 #define RSTMUX_OMODE8_SHIFT		0x1
83 #define RSTMUX_OMODE8_MASK		(0x7 << 1)
84 #define RSTMUX_OMODE8_DEV_RESET		0x2
85 #define RSTMUX_OMODE8_INT		0x3
86 #define RSTMUX_OMODE8_INT_AND_DEV_RESET	0x4
87 
88 /* DEVSTAT register definition */
89 #define KS2_DEVSTAT_REFCLK_SHIFT	 7
90 #define KS2_DEVSTAT_REFCLK_MASK		(0x7 << 7)
91 
92 /* GPMC */
93 #define KS2_GPMC_BASE			0x21818000
94 
95 /* SYSCLK indexes */
96 #define SYSCLK_19MHz	0
97 #define SYSCLK_24MHz	1
98 #define SYSCLK_25MHz	2
99 #define SYSCLK_26MHz	3
100 #define MAX_SYSCLK	4
101 
102 #ifndef __ASSEMBLY__
103 static inline u8 get_sysclk_index(void)
104 {
105 	u32 dev_stat = __raw_readl(KS2_DEVSTAT);
106 	return (dev_stat & KS2_DEVSTAT_REFCLK_MASK) >> KS2_DEVSTAT_REFCLK_SHIFT;
107 }
108 #endif
109 #endif /* __ASM_ARCH_HARDWARE_K2G_H */
110