1 /*
2  * K2G: SoC definitions
3  *
4  * (C) Copyright 2015
5  *     Texas Instruments Incorporated, <www.ti.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9 
10 #ifndef __ASM_ARCH_HARDWARE_K2G_H
11 #define __ASM_ARCH_HARDWARE_K2G_H
12 
13 #define KS2_NUM_DSPS			1
14 
15 /* Power and Sleep Controller (PSC) Domains */
16 #define KS2_LPSC_ALWAYSON		0
17 #define KS2_LPSC_PMMC			1
18 #define KS2_LPSC_DEBUG			2
19 #define KS2_LPSC_NSS			3
20 #define KS2_LPSC_SA			4
21 #define KS2_LPSC_TERANET		5
22 #define KS2_LPSC_SYS_COMP		6
23 #define KS2_LPSC_QSPI			7
24 #define KS2_LPSC_MMC			8
25 #define KS2_LPSC_GPMC			9
26 #define KS2_LPSC_MLB			11
27 #define KS2_LPSC_EHRPWM			12
28 #define KS2_LPSC_EQEP			13
29 #define KS2_LPSC_ECAP			14
30 #define KS2_LPSC_MCASP			15
31 #define KS2_LPSC_SR			16
32 #define KS2_LPSC_MSMC			17
33 #ifdef KS2_LPSC_GEM_0
34 #undef KS2_LPSC_GEM_0
35 #endif
36 #define KS2_LPSC_GEM_0			18
37 #define KS2_LPSC_ARM			19
38 #define KS2_LPSC_ASRC			20
39 #define KS2_LPSC_ICSS			21
40 #define KS2_LPSC_DSS			23
41 #define KS2_LPSC_PCIE			24
42 #define KS2_LPSC_USB_0			25
43 #define KS2_LPSC_USB			KS2_LPSC_USB_0
44 #define KS2_LPSC_USB_1			26
45 #define KS2_LPSC_DDR3			27
46 #define KS2_LPSC_SPARE0_LPSC0		28
47 #define KS2_LPSC_SPARE0_LPSC1		29
48 #define KS2_LPSC_SPARE1_LPSC0		30
49 #define KS2_LPSC_SPARE1_LPSC1		31
50 
51 #define KS2_LPSC_CPGMAC			KS2_LPSC_NSS
52 #define KS2_LPSC_CRYPTO			KS2_LPSC_SA
53 
54 /* SGMII SerDes */
55 #define KS2_LANES_PER_SGMII_SERDES	4
56 
57 /* NETCP pktdma */
58 #define KS2_NETCP_PDMA_CTRL_BASE	0x04010000
59 #define KS2_NETCP_PDMA_TX_BASE		0x04011000
60 #define KS2_NETCP_PDMA_TX_CH_NUM	21
61 #define KS2_NETCP_PDMA_RX_BASE		0x04012000
62 #define KS2_NETCP_PDMA_RX_CH_NUM	32
63 #define KS2_NETCP_PDMA_SCHED_BASE	0x04010100
64 #define KS2_NETCP_PDMA_RX_FLOW_BASE	0x04013000
65 #define KS2_NETCP_PDMA_RX_FLOW_NUM	32
66 #define KS2_NETCP_PDMA_TX_SND_QUEUE	5
67 
68 /* NETCP */
69 #define KS2_NETCP_BASE			0x04000000
70 
71 #define K2G_GPIO0_BASE			0X02603000
72 #define K2G_GPIO1_BASE			0X0260a000
73 #define K2G_GPIO1_BANK2_BASE		K2G_GPIO1_BASE + 0x38
74 #define K2G_GPIO_DIR_OFFSET		0x0
75 #define K2G_GPIO_SETDATA_OFFSET		0x8
76 
77 /* BOOTCFG RESETMUX8 */
78 #define KS2_RSTMUX8			(KS2_DEVICE_STATE_CTRL_BASE + 0x328)
79 
80 /* RESETMUX register definitions */
81 #define RSTMUX_LOCK8_SHIFT		0x0
82 #define RSTMUX_LOCK8_MASK		(0x1 << 0)
83 #define RSTMUX_OMODE8_SHIFT		0x1
84 #define RSTMUX_OMODE8_MASK		(0x7 << 1)
85 #define RSTMUX_OMODE8_DEV_RESET		0x2
86 #define RSTMUX_OMODE8_INT		0x3
87 #define RSTMUX_OMODE8_INT_AND_DEV_RESET	0x4
88 
89 #endif /* __ASM_ARCH_HARDWARE_K2G_H */
90