1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2dc7de222SMasahiro Yamada /* 3dc7de222SMasahiro Yamada * K2E: SoC definitions 4dc7de222SMasahiro Yamada * 5dc7de222SMasahiro Yamada * (C) Copyright 2012-2014 6dc7de222SMasahiro Yamada * Texas Instruments Incorporated, <www.ti.com> 7dc7de222SMasahiro Yamada */ 8dc7de222SMasahiro Yamada 9dc7de222SMasahiro Yamada #ifndef __ASM_ARCH_HARDWARE_K2E_H 10dc7de222SMasahiro Yamada #define __ASM_ARCH_HARDWARE_K2E_H 11dc7de222SMasahiro Yamada 12dc7de222SMasahiro Yamada /* PA SS Registers */ 13dc7de222SMasahiro Yamada #define KS2_PASS_BASE 0x24000000 14dc7de222SMasahiro Yamada 15dc7de222SMasahiro Yamada /* Power and Sleep Controller (PSC) Domains */ 16dc7de222SMasahiro Yamada #define KS2_LPSC_MOD_RST 0 17dc7de222SMasahiro Yamada #define KS2_LPSC_USB_1 1 18dc7de222SMasahiro Yamada #define KS2_LPSC_USB 2 19dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF25_SPI 3 20dc7de222SMasahiro Yamada #define KS2_LPSC_TSIP 4 21dc7de222SMasahiro Yamada #define KS2_LPSC_DEBUGSS_TRC 5 22dc7de222SMasahiro Yamada #define KS2_LPSC_TETB_TRC 6 23dc7de222SMasahiro Yamada #define KS2_LPSC_PKTPROC 7 24dc7de222SMasahiro Yamada #define KS2_LPSC_PA KS2_LPSC_PKTPROC 25dc7de222SMasahiro Yamada #define KS2_LPSC_SGMII 8 26dc7de222SMasahiro Yamada #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 27dc7de222SMasahiro Yamada #define KS2_LPSC_CRYPTO 9 28dc7de222SMasahiro Yamada #define KS2_LPSC_PCIE 10 29dc7de222SMasahiro Yamada #define KS2_LPSC_VUSR0 12 30dc7de222SMasahiro Yamada #define KS2_LPSC_CHIP_SRSS 13 31dc7de222SMasahiro Yamada #define KS2_LPSC_MSMC 14 32dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF4F_DDR3 23 33dc7de222SMasahiro Yamada #define KS2_LPSC_PCIE_1 27 34dc7de222SMasahiro Yamada #define KS2_LPSC_XGE 50 35dc7de222SMasahiro Yamada 36dc7de222SMasahiro Yamada /* Chip Interrupt Controller */ 37dc7de222SMasahiro Yamada #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ 38dc7de222SMasahiro Yamada #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ 39dc7de222SMasahiro Yamada 40dc7de222SMasahiro Yamada /* SGMII SerDes */ 41dc7de222SMasahiro Yamada #define KS2_SGMII_SERDES2_BASE 0x02324000 42dc7de222SMasahiro Yamada #define KS2_LANES_PER_SGMII_SERDES 4 43dc7de222SMasahiro Yamada 44dc7de222SMasahiro Yamada /* Number of DSP cores */ 45dc7de222SMasahiro Yamada #define KS2_NUM_DSPS 1 46dc7de222SMasahiro Yamada 47dc7de222SMasahiro Yamada /* NETCP pktdma */ 48dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 49dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_BASE 0x24187000 50dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_CH_NUM 21 51dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_BASE 0x24188000 52dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_CH_NUM 91 53dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 54dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 55dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 56dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_SND_QUEUE 896 57dc7de222SMasahiro Yamada 58dc7de222SMasahiro Yamada /* NETCP */ 59dc7de222SMasahiro Yamada #define KS2_NETCP_BASE 0x24000000 60dc7de222SMasahiro Yamada 61dc7de222SMasahiro Yamada #endif 62