1 /* 2 * keystone2: common pll clock definitions 3 * (C) Copyright 2012-2014 4 * Texas Instruments Incorporated, <www.ti.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _CLOCK_DEFS_H_ 10 #define _CLOCK_DEFS_H_ 11 12 #include <asm/arch/hardware.h> 13 14 #define BIT(x) (1 << (x)) 15 16 /* PLL Control Registers */ 17 struct pllctl_regs { 18 u32 ctl; /* 00 */ 19 u32 ocsel; /* 04 */ 20 u32 secctl; /* 08 */ 21 u32 resv0; 22 u32 mult; /* 10 */ 23 u32 prediv; /* 14 */ 24 u32 div1; /* 18 */ 25 u32 div2; /* 1c */ 26 u32 div3; /* 20 */ 27 u32 oscdiv1; /* 24 */ 28 u32 resv1; /* 28 */ 29 u32 bpdiv; /* 2c */ 30 u32 wakeup; /* 30 */ 31 u32 resv2; 32 u32 cmd; /* 38 */ 33 u32 stat; /* 3c */ 34 u32 alnctl; /* 40 */ 35 u32 dchange; /* 44 */ 36 u32 cken; /* 48 */ 37 u32 ckstat; /* 4c */ 38 u32 systat; /* 50 */ 39 u32 ckctl; /* 54 */ 40 u32 resv3[2]; 41 u32 div4; /* 60 */ 42 u32 div5; /* 64 */ 43 u32 div6; /* 68 */ 44 u32 div7; /* 6c */ 45 u32 div8; /* 70 */ 46 u32 div9; /* 74 */ 47 u32 div10; /* 78 */ 48 u32 div11; /* 7c */ 49 u32 div12; /* 80 */ 50 }; 51 52 static struct pllctl_regs *pllctl_regs[] = { 53 (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100) 54 }; 55 56 #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) 57 #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) 58 #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) 59 60 #define pllctl_reg_rmw(pll, reg, mask, val) \ 61 pllctl_reg_write(pll, reg, \ 62 (pllctl_reg_read(pll, reg) & ~(mask)) | val) 63 64 #define pllctl_reg_setbits(pll, reg, mask) \ 65 pllctl_reg_rmw(pll, reg, 0, mask) 66 67 #define pllctl_reg_clrbits(pll, reg, mask) \ 68 pllctl_reg_rmw(pll, reg, mask, 0) 69 70 #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) 71 72 /* PLLCTL Bits */ 73 #define PLLCTL_BYPASS BIT(23) 74 #define PLL_PLLRST BIT(14) 75 #define PLLCTL_PAPLL BIT(13) 76 #define PLLCTL_CLKMODE BIT(8) 77 #define PLLCTL_PLLSELB BIT(7) 78 #define PLLCTL_ENSAT BIT(6) 79 #define PLLCTL_PLLENSRC BIT(5) 80 #define PLLCTL_PLLDIS BIT(4) 81 #define PLLCTL_PLLRST BIT(3) 82 #define PLLCTL_PLLPWRDN BIT(1) 83 #define PLLCTL_PLLEN BIT(0) 84 #define PLLSTAT_GO BIT(0) 85 86 #define MAIN_ENSAT_OFFSET 6 87 88 #define PLLDIV_ENABLE BIT(15) 89 90 #define PLL_DIV_MASK 0x3f 91 #define PLL_MULT_MASK 0x1fff 92 #define PLL_MULT_SHIFT 6 93 #define PLLM_MULT_HI_MASK 0x7f 94 #define PLLM_MULT_HI_SHIFT 12 95 #define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT) 96 #define PLLM_MULT_LO_MASK 0x3f 97 #define PLL_CLKOD_MASK 0xf 98 #define PLL_CLKOD_SHIFT 19 99 #define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT) 100 #define PLL_BWADJ_LO_MASK 0xff 101 #define PLL_BWADJ_LO_SHIFT 24 102 #define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) 103 #define PLL_BWADJ_HI_MASK 0xf 104 105 #define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) 106 #define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) 107 #define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) 108 #define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) 109 #define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) 110 111 #endif /* _CLOCK_DEFS_H_ */ 112