1 /*
2  * Keystone2: DDR3 SPD configuration
3  *
4  * (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8 
9 #include <common.h>
10 
11 #include <i2c.h>
12 #include <ddr_spd.h>
13 #include <asm/arch/ddr3.h>
14 #include <asm/arch/hardware.h>
15 
16 #define DUMP_DDR_CONFIG			0	/* set to 1 to debug */
17 #define debug_ddr_cfg(fmt, args...)					\
18 		   debug_cond(DUMP_DDR_CONFIG, fmt, ##args)
19 
20 static void dump_phy_config(struct ddr3_phy_config *ptr)
21 {
22 	debug_ddr_cfg("\npllcr		0x%08X\n", ptr->pllcr);
23 	debug_ddr_cfg("pgcr1_mask	0x%08X\n", ptr->pgcr1_mask);
24 	debug_ddr_cfg("pgcr1_val	0x%08X\n", ptr->pgcr1_val);
25 	debug_ddr_cfg("ptr0		0x%08X\n", ptr->ptr0);
26 	debug_ddr_cfg("ptr1		0x%08X\n", ptr->ptr1);
27 	debug_ddr_cfg("ptr2		0x%08X\n", ptr->ptr2);
28 	debug_ddr_cfg("ptr3		0x%08X\n", ptr->ptr3);
29 	debug_ddr_cfg("ptr4		0x%08X\n", ptr->ptr4);
30 	debug_ddr_cfg("dcr_mask		0x%08X\n", ptr->dcr_mask);
31 	debug_ddr_cfg("dcr_val		0x%08X\n", ptr->dcr_val);
32 	debug_ddr_cfg("dtpr0		0x%08X\n", ptr->dtpr0);
33 	debug_ddr_cfg("dtpr1		0x%08X\n", ptr->dtpr1);
34 	debug_ddr_cfg("dtpr2		0x%08X\n", ptr->dtpr2);
35 	debug_ddr_cfg("mr0		0x%08X\n", ptr->mr0);
36 	debug_ddr_cfg("mr1		0x%08X\n", ptr->mr1);
37 	debug_ddr_cfg("mr2		0x%08X\n", ptr->mr2);
38 	debug_ddr_cfg("dtcr		0x%08X\n", ptr->dtcr);
39 	debug_ddr_cfg("pgcr2		0x%08X\n", ptr->pgcr2);
40 	debug_ddr_cfg("zq0cr1		0x%08X\n", ptr->zq0cr1);
41 	debug_ddr_cfg("zq1cr1		0x%08X\n", ptr->zq1cr1);
42 	debug_ddr_cfg("zq2cr1		0x%08X\n", ptr->zq2cr1);
43 	debug_ddr_cfg("pir_v1		0x%08X\n", ptr->pir_v1);
44 	debug_ddr_cfg("pir_v2		0x%08X\n\n", ptr->pir_v2);
45 };
46 
47 static void dump_emif_config(struct ddr3_emif_config *ptr)
48 {
49 	debug_ddr_cfg("\nsdcfg		0x%08X\n", ptr->sdcfg);
50 	debug_ddr_cfg("sdtim1		0x%08X\n", ptr->sdtim1);
51 	debug_ddr_cfg("sdtim2		0x%08X\n", ptr->sdtim2);
52 	debug_ddr_cfg("sdtim3		0x%08X\n", ptr->sdtim3);
53 	debug_ddr_cfg("sdtim4		0x%08X\n", ptr->sdtim4);
54 	debug_ddr_cfg("zqcfg		0x%08X\n", ptr->zqcfg);
55 	debug_ddr_cfg("sdrfc		0x%08X\n\n", ptr->sdrfc);
56 };
57 
58 #define TEMP NORMAL_TEMP
59 #define VBUS_CLKPERIOD 1.875 /* Corresponds to vbus=533MHz, */
60 #define PLLGS_VAL	(4000.0 / VBUS_CLKPERIOD) /* 4 us */
61 #define PLLPD_VAL	(1000.0 / VBUS_CLKPERIOD) /* 1 us */
62 #define PLLLOCK_VAL	(100000.0 / VBUS_CLKPERIOD) /* 100 us */
63 #define PLLRST_VAL	(9000.0 / VBUS_CLKPERIOD) /* 9 us */
64 #define PHYRST_VAL	0x10
65 #define DDR_TERM RZQ_4_TERM
66 #define SDRAM_DRIVE RZQ_7_IMP
67 #define DYN_ODT ODT_DISABLE
68 
69 enum srt {
70 	NORMAL_TEMP,
71 	EXTENDED_TEMP
72 };
73 
74 enum out_impedance {
75 	RZQ_6_IMP = 0,
76 	RZQ_7_IMP
77 };
78 
79 enum die_term {
80 	ODT_DISABLE = 0,
81 	RZQ_4_TERM,
82 	RZQ_2_TERM,
83 	RZQ_6_TERM,
84 	RZQ_12_TERM,
85 	RZQ_8_TERM
86 };
87 
88 struct ddr3_sodimm {
89 	u32 t_ck;
90 	u32 freqsel;
91 	u32 t_xp;
92 	u32 t_cke;
93 	u32 t_pllpd;
94 	u32 t_pllgs;
95 	u32 t_phyrst;
96 	u32 t_plllock;
97 	u32 t_pllrst;
98 	u32 t_rfc;
99 	u32 t_xs;
100 	u32 t_dinit0;
101 	u32 t_dinit1;
102 	u32 t_dinit2;
103 	u32 t_dinit3;
104 	u32 t_rtp;
105 	u32 t_wtr;
106 	u32 t_rp;
107 	u32 t_rcd;
108 	u32 t_ras;
109 	u32 t_rrd;
110 	u32 t_rc;
111 	u32 t_faw;
112 	u32 t_mrd;
113 	u32 t_mod;
114 	u32 t_wlo;
115 	u32 t_wlmrd;
116 	u32 t_xsdll;
117 	u32 t_xpdll;
118 	u32 t_ckesr;
119 	u32 t_dllk;
120 	u32 t_wr;
121 	u32 t_wr_bin;
122 	u32 cas;
123 	u32 cwl;
124 	u32 asr;
125 	u32 pasr;
126 	u32 t_refprd;
127 	u8 sdram_type;
128 	u8 ibank;
129 	u8 pagesize;
130 	u8 t_rrd2;
131 	u8 t_ras_max;
132 	u8 t_zqcs;
133 	u32 refresh_rate;
134 	u8 t_csta;
135 
136 	u8 rank;
137 	u8 mirrored;
138 	u8 buswidth;
139 };
140 
141 static u8 cas_latancy(u16 temp)
142 {
143 	int loop;
144 	u8 cas_bin = 0;
145 
146 	for (loop = 0; loop < 32; loop += 2, temp >>= 1) {
147 		if (temp & 0x0001)
148 			cas_bin = (loop > 15) ? loop - 15 : loop;
149 	}
150 
151 	return cas_bin;
152 }
153 
154 static int ddr3_get_size_in_mb(ddr3_spd_eeprom_t *buf)
155 {
156 	return (((buf->organization & 0x38) >> 3) + 1) *
157 		(256 << (buf->density_banks & 0xf));
158 }
159 
160 static int ddrtimingcalculation(ddr3_spd_eeprom_t *buf, struct ddr3_sodimm *spd,
161 				struct ddr3_spd_cb *spd_cb)
162 {
163 	u32 mtb, clk_freq;
164 
165 	if ((buf->mem_type != 0x0b) ||
166 	    ((buf->density_banks & 0x70) != 0x00))
167 		return 1;
168 
169 	spd->sdram_type = 0x03;
170 	spd->ibank = 0x03;
171 
172 	mtb = buf->mtb_dividend * 1000 / buf->mtb_divisor;
173 
174 	spd->t_ck = buf->tck_min * mtb;
175 
176 	spd_cb->ddrspdclock = 2000000 / spd->t_ck;
177 	clk_freq = spd_cb->ddrspdclock / 2;
178 
179 	spd->rank = ((buf->organization & 0x38) >> 3) + 1;
180 	if (spd->rank > 2)
181 		return 1;
182 
183 	spd->pagesize = (buf->addressing & 0x07) + 1;
184 	if (spd->pagesize > 3)
185 		return 1;
186 
187 	spd->buswidth = 8 << (buf->bus_width & 0x7);
188 	if ((spd->buswidth < 16) || (spd->buswidth > 64))
189 		return 1;
190 
191 	spd->mirrored = buf->mod_section.unbuffered.addr_mapping & 1;
192 
193 	printf("DDR3A Speed will be configured for %d Operation.\n",
194 	       spd_cb->ddrspdclock);
195 	if (spd_cb->ddrspdclock == 1333) {
196 		spd->t_xp = ((3 * spd->t_ck) > 6000) ?
197 			3 : ((5999 / spd->t_ck) + 1);
198 		spd->t_cke = ((3 * spd->t_ck) > 5625) ?
199 			3 : ((5624 / spd->t_ck) + 1);
200 	} else if (spd_cb->ddrspdclock == 1600) {
201 		spd->t_xp = ((3 * spd->t_ck) > 6000) ?
202 			3 : ((5999 / spd->t_ck) + 1);
203 		spd->t_cke = ((3 * spd->t_ck) > 5000) ?
204 			3 : ((4999 / spd->t_ck) + 1);
205 	} else {
206 		printf("Unsupported DDR3 speed %d\n", spd_cb->ddrspdclock);
207 		return 1;
208 	}
209 
210 	spd->t_xpdll = (spd->t_ck > 2400) ? 10 : 24000 / spd->t_ck;
211 	spd->t_ckesr = spd->t_cke + 1;
212 
213 	/* SPD Calculated Values */
214 	spd->cas = cas_latancy((buf->caslat_msb << 8) |
215 			       buf->caslat_lsb);
216 
217 	spd->t_wr = (buf->twr_min * mtb) / spd->t_ck;
218 	spd->t_wr_bin = (spd->t_wr / 2) & 0x07;
219 
220 	spd->t_rcd = ((buf->trcd_min * mtb) - 1) / spd->t_ck + 1;
221 	spd->t_rrd = ((buf->trrd_min * mtb) - 1) / spd->t_ck + 1;
222 	spd->t_rp  = (((buf->trp_min * mtb) - 1) / spd->t_ck) + 1;
223 
224 	spd->t_ras = (((buf->tras_trc_ext & 0x0f) << 8 | buf->tras_min_lsb) *
225 		      mtb) / spd->t_ck;
226 
227 	spd->t_rc = (((((buf->tras_trc_ext & 0xf0) << 4) | buf->trc_min_lsb) *
228 		      mtb) - 1) / spd->t_ck + 1;
229 
230 	spd->t_rfc = (buf->trfc_min_lsb | (buf->trfc_min_msb << 8)) * mtb /
231 		1000;
232 	spd->t_wtr = (buf->twtr_min * mtb) / spd->t_ck;
233 	spd->t_rtp = (buf->trtp_min * mtb) / spd->t_ck;
234 
235 	spd->t_xs  = (((spd->t_rfc + 10) * 1000) / spd->t_ck);
236 	spd->t_rfc = ((spd->t_rfc * 1000) - 1) / spd->t_ck + 1;
237 
238 	spd->t_faw = (((buf->tfaw_msb << 8) | buf->tfaw_min) * mtb) / spd->t_ck;
239 	spd->t_rrd2 = ((((buf->tfaw_msb << 8) |
240 			 buf->tfaw_min) * mtb) / (4 * spd->t_ck)) - 1;
241 
242 	/* Hard-coded values */
243 	spd->t_mrd = 0x00;
244 	spd->t_mod = 0x00;
245 	spd->t_wlo = 0x0C;
246 	spd->t_wlmrd = 0x28;
247 	spd->t_xsdll = 0x200;
248 	spd->t_ras_max = 0x0F;
249 	spd->t_csta = 0x05;
250 	spd->t_dllk = 0x200;
251 
252 	/* CAS Write Latency */
253 	if (spd->t_ck >= 2500)
254 		spd->cwl = 0;
255 	else if (spd->t_ck >= 1875)
256 		spd->cwl = 1;
257 	else if (spd->t_ck >= 1500)
258 		spd->cwl = 2;
259 	else if (spd->t_ck >= 1250)
260 		spd->cwl = 3;
261 	else if (spd->t_ck >= 1071)
262 		spd->cwl = 4;
263 	else
264 		spd->cwl = 5;
265 
266 	/* SD:RAM Thermal and Refresh Options */
267 	spd->asr = (buf->therm_ref_opt & 0x04) >> 2;
268 	spd->pasr = (buf->therm_ref_opt & 0x80) >> 7;
269 	spd->t_zqcs = 64;
270 
271 	spd->t_refprd = (TEMP == NORMAL_TEMP) ? 7812500 : 3906250;
272 	spd->t_refprd = spd->t_refprd / spd->t_ck;
273 
274 	spd->refresh_rate = spd->t_refprd;
275 	spd->t_refprd = spd->t_refprd * 5;
276 
277 	/* Set MISC PHY space registers fields */
278 	if ((clk_freq / 2) >= 166 && (clk_freq / 2 < 275))
279 		spd->freqsel = 0x03;
280 	else if ((clk_freq / 2) > 225 && (clk_freq / 2 < 385))
281 		spd->freqsel = 0x01;
282 	else if ((clk_freq / 2) > 335 && (clk_freq / 2 < 534))
283 		spd->freqsel = 0x00;
284 
285 	spd->t_dinit0 = 500000000 / spd->t_ck; /* CKE low time 500 us */
286 	spd->t_dinit1 = spd->t_xs;
287 	spd->t_dinit2 = 200000000 / spd->t_ck; /* Reset low time 200 us */
288 	/* Time from ZQ initialization command to first command (1 us) */
289 	spd->t_dinit3 =  1000000 / spd->t_ck;
290 
291 	spd->t_pllgs = PLLGS_VAL + 1;
292 	spd->t_pllpd = PLLPD_VAL + 1;
293 	spd->t_plllock = PLLLOCK_VAL + 1;
294 	spd->t_pllrst = PLLRST_VAL;
295 	spd->t_phyrst = PHYRST_VAL;
296 
297 	spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024;
298 
299 	return 0;
300 }
301 
302 static void init_ddr3param(struct ddr3_spd_cb *spd_cb,
303 			   struct ddr3_sodimm *spd)
304 {
305 	spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13;
306 	spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK);
307 	spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23));
308 	spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) |
309 		((spd->t_pllgs & 0x7fff) << 6) | (spd->t_phyrst & 0x3f);
310 	spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) |
311 		(spd->t_pllrst & 0x1fff);
312 	spd_cb->phy_cfg.ptr2 = 0;
313 	spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) |
314 		(spd->t_dinit0 & 0xfffff);
315 	spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) |
316 		(spd->t_dinit2 & 0x3ffff);
317 
318 	spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK;
319 	spd_cb->phy_cfg.dcr_val = 1 << 10;
320 
321 	if (spd->mirrored) {
322 		spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK;
323 		spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29);
324 	}
325 
326 	spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 |
327 		(spd->t_rrd & 0xf) << 22 |
328 		(spd->t_ras & 0x3f) << 16 | (spd->t_rcd & 0xf) << 12 |
329 		(spd->t_rp & 0xf) << 8 | (spd->t_wtr & 0xf) << 4 |
330 		(spd->t_rtp & 0xf);
331 	spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 |
332 		(spd->t_wlmrd & 0x3f) << 20 | (spd->t_rfc & 0x1ff) << 11 |
333 		(spd->t_faw & 0x3f) << 5 | (spd->t_mod & 0x7) << 2 |
334 		(spd->t_mrd & 0x3);
335 
336 	spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 |
337 		(spd->t_dllk & 0x3ff) << 19 | (spd->t_ckesr & 0xf) << 15;
338 
339 	spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ?
340 				   spd->t_xp : spd->t_xpdll) &
341 				  0x1f) << 10;
342 
343 	spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ?
344 			      spd->t_xs : spd->t_xsdll) &
345 			     0x3ff);
346 
347 	spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 |
348 		0 << 7 | ((spd->cas & 0x0E) >> 1) << 4 | 0 << 3 |
349 		(spd->cas & 0x01) << 2;
350 
351 	spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 |
352 		((DDR_TERM >> 2) & 1) << 9 | ((DDR_TERM >> 1) & 1) << 6 |
353 		(DDR_TERM & 0x1) << 2 | ((SDRAM_DRIVE >> 1) & 1) << 5 |
354 		(SDRAM_DRIVE & 1) << 1 | 0 << 0;
355 
356 	spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 |
357 		(spd->cwl & 7) << 3 | (spd->pasr & 7);
358 
359 	spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7;
360 	spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff);
361 
362 	spd_cb->phy_cfg.zq0cr1 = 0x0000005D;
363 	spd_cb->phy_cfg.zq1cr1 = 0x0000005B;
364 	spd_cb->phy_cfg.zq2cr1 = 0x0000005B;
365 
366 	spd_cb->phy_cfg.pir_v1 = 0x00000033;
367 	spd_cb->phy_cfg.pir_v2 = 0x0000FF81;
368 
369 	/* EMIF Registers */
370 	spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 |
371 		(DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 |
372 		(spd->cas & 0xf) << 8 | (spd->ibank & 3) << 5 |
373 		(spd->buswidth & 3) << 12 | (spd->pagesize & 3);
374 
375 	if (spd->rank == 2)
376 		spd_cb->emif_cfg.sdcfg |= 1 << 3;
377 
378 	spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 |
379 		((spd->t_ras - 1) & 0x7f) << 18 |
380 		((spd->t_rc - 1) & 0xff) << 10 |
381 		(spd->t_rrd2 & 0x3f) << 4  |
382 		((spd->t_wtr - 1) & 0xf);
383 
384 	spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 |
385 		((spd->t_rcd - 1) & 0x1f);
386 
387 	spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 |
388 		((spd->t_xs - 1) & 0x3ff) << 18 |
389 		((spd->t_xsdll - 1) & 0x3ff) << 8 |
390 		((spd->t_rtp - 1) & 0xf) << 4 | ((spd->t_cke) & 0xf);
391 
392 	spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 |
393 		((spd->t_ckesr - 1) & 0xf) << 24 |
394 		((spd->t_zqcs - 1) & 0xff) << 16 |
395 		((spd->t_rfc - 1) & 0x3ff) << 4 |
396 		(spd->t_ras_max & 0xf);
397 
398 	spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff;
399 
400 	/* TODO zqcfg value fixed ,May be required correction for K2E evm. */
401 	spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200;
402 }
403 
404 static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
405 {
406 	int ret;
407 	int old_bus;
408 
409 	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
410 
411 	old_bus = i2c_get_bus_num();
412 	i2c_set_bus_num(1);
413 
414 	ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256);
415 
416 	i2c_set_bus_num(old_bus);
417 
418 	if (ret) {
419 		printf("Cannot read DIMM params\n");
420 		return 1;
421 	}
422 
423 	if (ddr3_spd_check(spd_params))
424 		return 1;
425 
426 	return 0;
427 }
428 
429 int ddr3_get_size(void)
430 {
431 	ddr3_spd_eeprom_t spd_params;
432 
433 	if (ddr3_read_spd(&spd_params))
434 		return 0;
435 
436 	return ddr3_get_size_in_mb(&spd_params) / 1024;
437 }
438 
439 int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb)
440 {
441 	struct ddr3_sodimm spd;
442 	ddr3_spd_eeprom_t spd_params;
443 
444 	memset(&spd, 0, sizeof(spd));
445 
446 	if (ddr3_read_spd(&spd_params))
447 		return 1;
448 
449 	if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) {
450 		printf("Timing caclulation error\n");
451 		return 1;
452 	}
453 
454 	strncpy(spd_cb->dimm_name, (char *)spd_params.mpart, 18);
455 	spd_cb->dimm_name[18] = '\0';
456 
457 	init_ddr3param(spd_cb, &spd);
458 
459 	dump_emif_config(&spd_cb->emif_cfg);
460 	dump_phy_config(&spd_cb->phy_cfg);
461 
462 	return 0;
463 }
464