1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Keystone2: DDR3 SPD configuration
4 *
5 * (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com>
6 */
7
8 #include <common.h>
9
10 #include <i2c.h>
11 #include <ddr_spd.h>
12 #include <asm/arch/ddr3.h>
13 #include <asm/arch/hardware.h>
14
15 #define DUMP_DDR_CONFIG 0 /* set to 1 to debug */
16 #define debug_ddr_cfg(fmt, args...) \
17 debug_cond(DUMP_DDR_CONFIG, fmt, ##args)
18
dump_phy_config(struct ddr3_phy_config * ptr)19 static void dump_phy_config(struct ddr3_phy_config *ptr)
20 {
21 debug_ddr_cfg("\npllcr 0x%08X\n", ptr->pllcr);
22 debug_ddr_cfg("pgcr1_mask 0x%08X\n", ptr->pgcr1_mask);
23 debug_ddr_cfg("pgcr1_val 0x%08X\n", ptr->pgcr1_val);
24 debug_ddr_cfg("ptr0 0x%08X\n", ptr->ptr0);
25 debug_ddr_cfg("ptr1 0x%08X\n", ptr->ptr1);
26 debug_ddr_cfg("ptr2 0x%08X\n", ptr->ptr2);
27 debug_ddr_cfg("ptr3 0x%08X\n", ptr->ptr3);
28 debug_ddr_cfg("ptr4 0x%08X\n", ptr->ptr4);
29 debug_ddr_cfg("dcr_mask 0x%08X\n", ptr->dcr_mask);
30 debug_ddr_cfg("dcr_val 0x%08X\n", ptr->dcr_val);
31 debug_ddr_cfg("dtpr0 0x%08X\n", ptr->dtpr0);
32 debug_ddr_cfg("dtpr1 0x%08X\n", ptr->dtpr1);
33 debug_ddr_cfg("dtpr2 0x%08X\n", ptr->dtpr2);
34 debug_ddr_cfg("mr0 0x%08X\n", ptr->mr0);
35 debug_ddr_cfg("mr1 0x%08X\n", ptr->mr1);
36 debug_ddr_cfg("mr2 0x%08X\n", ptr->mr2);
37 debug_ddr_cfg("dtcr 0x%08X\n", ptr->dtcr);
38 debug_ddr_cfg("pgcr2 0x%08X\n", ptr->pgcr2);
39 debug_ddr_cfg("zq0cr1 0x%08X\n", ptr->zq0cr1);
40 debug_ddr_cfg("zq1cr1 0x%08X\n", ptr->zq1cr1);
41 debug_ddr_cfg("zq2cr1 0x%08X\n", ptr->zq2cr1);
42 debug_ddr_cfg("pir_v1 0x%08X\n", ptr->pir_v1);
43 debug_ddr_cfg("pir_v2 0x%08X\n\n", ptr->pir_v2);
44 };
45
dump_emif_config(struct ddr3_emif_config * ptr)46 static void dump_emif_config(struct ddr3_emif_config *ptr)
47 {
48 debug_ddr_cfg("\nsdcfg 0x%08X\n", ptr->sdcfg);
49 debug_ddr_cfg("sdtim1 0x%08X\n", ptr->sdtim1);
50 debug_ddr_cfg("sdtim2 0x%08X\n", ptr->sdtim2);
51 debug_ddr_cfg("sdtim3 0x%08X\n", ptr->sdtim3);
52 debug_ddr_cfg("sdtim4 0x%08X\n", ptr->sdtim4);
53 debug_ddr_cfg("zqcfg 0x%08X\n", ptr->zqcfg);
54 debug_ddr_cfg("sdrfc 0x%08X\n\n", ptr->sdrfc);
55 };
56
57 #define TEMP NORMAL_TEMP
58 #define VBUS_CLKPERIOD 1.875 /* Corresponds to vbus=533MHz, */
59 #define PLLGS_VAL (4000.0 / VBUS_CLKPERIOD) /* 4 us */
60 #define PLLPD_VAL (1000.0 / VBUS_CLKPERIOD) /* 1 us */
61 #define PLLLOCK_VAL (100000.0 / VBUS_CLKPERIOD) /* 100 us */
62 #define PLLRST_VAL (9000.0 / VBUS_CLKPERIOD) /* 9 us */
63 #define PHYRST_VAL 0x10
64 #define DDR_TERM RZQ_4_TERM
65 #define SDRAM_DRIVE RZQ_7_IMP
66 #define DYN_ODT ODT_DISABLE
67
68 enum srt {
69 NORMAL_TEMP,
70 EXTENDED_TEMP
71 };
72
73 enum out_impedance {
74 RZQ_6_IMP = 0,
75 RZQ_7_IMP
76 };
77
78 enum die_term {
79 ODT_DISABLE = 0,
80 RZQ_4_TERM,
81 RZQ_2_TERM,
82 RZQ_6_TERM,
83 RZQ_12_TERM,
84 RZQ_8_TERM
85 };
86
87 struct ddr3_sodimm {
88 u32 t_ck;
89 u32 freqsel;
90 u32 t_xp;
91 u32 t_cke;
92 u32 t_pllpd;
93 u32 t_pllgs;
94 u32 t_phyrst;
95 u32 t_plllock;
96 u32 t_pllrst;
97 u32 t_rfc;
98 u32 t_xs;
99 u32 t_dinit0;
100 u32 t_dinit1;
101 u32 t_dinit2;
102 u32 t_dinit3;
103 u32 t_rtp;
104 u32 t_wtr;
105 u32 t_rp;
106 u32 t_rcd;
107 u32 t_ras;
108 u32 t_rrd;
109 u32 t_rc;
110 u32 t_faw;
111 u32 t_mrd;
112 u32 t_mod;
113 u32 t_wlo;
114 u32 t_wlmrd;
115 u32 t_xsdll;
116 u32 t_xpdll;
117 u32 t_ckesr;
118 u32 t_dllk;
119 u32 t_wr;
120 u32 t_wr_bin;
121 u32 cas;
122 u32 cwl;
123 u32 asr;
124 u32 pasr;
125 u32 t_refprd;
126 u8 sdram_type;
127 u8 ibank;
128 u8 pagesize;
129 u8 t_rrd2;
130 u8 t_ras_max;
131 u8 t_zqcs;
132 u32 refresh_rate;
133 u8 t_csta;
134
135 u8 rank;
136 u8 mirrored;
137 u8 buswidth;
138 };
139
cas_latancy(u16 temp)140 static u8 cas_latancy(u16 temp)
141 {
142 int loop;
143 u8 cas_bin = 0;
144
145 for (loop = 0; loop < 32; loop += 2, temp >>= 1) {
146 if (temp & 0x0001)
147 cas_bin = (loop > 15) ? loop - 15 : loop;
148 }
149
150 return cas_bin;
151 }
152
ddr3_get_size_in_mb(ddr3_spd_eeprom_t * buf)153 static int ddr3_get_size_in_mb(ddr3_spd_eeprom_t *buf)
154 {
155 return (((buf->organization & 0x38) >> 3) + 1) *
156 (256 << (buf->density_banks & 0xf));
157 }
158
ddrtimingcalculation(ddr3_spd_eeprom_t * buf,struct ddr3_sodimm * spd,struct ddr3_spd_cb * spd_cb)159 static int ddrtimingcalculation(ddr3_spd_eeprom_t *buf, struct ddr3_sodimm *spd,
160 struct ddr3_spd_cb *spd_cb)
161 {
162 u32 mtb, clk_freq;
163
164 if ((buf->mem_type != 0x0b) ||
165 ((buf->density_banks & 0x70) != 0x00))
166 return 1;
167
168 spd->sdram_type = 0x03;
169 spd->ibank = 0x03;
170
171 mtb = buf->mtb_dividend * 1000 / buf->mtb_divisor;
172
173 spd->t_ck = buf->tck_min * mtb;
174
175 spd_cb->ddrspdclock = 2000000 / spd->t_ck;
176 clk_freq = spd_cb->ddrspdclock / 2;
177
178 spd->rank = ((buf->organization & 0x38) >> 3) + 1;
179 if (spd->rank > 2)
180 return 1;
181
182 spd->pagesize = (buf->addressing & 0x07) + 1;
183 if (spd->pagesize > 3)
184 return 1;
185
186 spd->buswidth = 8 << (buf->bus_width & 0x7);
187 if ((spd->buswidth < 16) || (spd->buswidth > 64))
188 return 1;
189
190 spd->mirrored = buf->mod_section.unbuffered.addr_mapping & 1;
191
192 printf("DDR3A Speed will be configured for %d Operation.\n",
193 spd_cb->ddrspdclock);
194 if (spd_cb->ddrspdclock == 1333) {
195 spd->t_xp = ((3 * spd->t_ck) > 6000) ?
196 3 : ((5999 / spd->t_ck) + 1);
197 spd->t_cke = ((3 * spd->t_ck) > 5625) ?
198 3 : ((5624 / spd->t_ck) + 1);
199 } else if (spd_cb->ddrspdclock == 1600) {
200 spd->t_xp = ((3 * spd->t_ck) > 6000) ?
201 3 : ((5999 / spd->t_ck) + 1);
202 spd->t_cke = ((3 * spd->t_ck) > 5000) ?
203 3 : ((4999 / spd->t_ck) + 1);
204 } else {
205 printf("Unsupported DDR3 speed %d\n", spd_cb->ddrspdclock);
206 return 1;
207 }
208
209 spd->t_xpdll = (spd->t_ck > 2400) ? 10 : 24000 / spd->t_ck;
210 spd->t_ckesr = spd->t_cke + 1;
211
212 /* SPD Calculated Values */
213 spd->cas = cas_latancy((buf->caslat_msb << 8) |
214 buf->caslat_lsb);
215
216 spd->t_wr = (buf->twr_min * mtb) / spd->t_ck;
217 spd->t_wr_bin = (spd->t_wr / 2) & 0x07;
218
219 spd->t_rcd = ((buf->trcd_min * mtb) - 1) / spd->t_ck + 1;
220 spd->t_rrd = ((buf->trrd_min * mtb) - 1) / spd->t_ck + 1;
221 spd->t_rp = (((buf->trp_min * mtb) - 1) / spd->t_ck) + 1;
222
223 spd->t_ras = (((buf->tras_trc_ext & 0x0f) << 8 | buf->tras_min_lsb) *
224 mtb) / spd->t_ck;
225
226 spd->t_rc = (((((buf->tras_trc_ext & 0xf0) << 4) | buf->trc_min_lsb) *
227 mtb) - 1) / spd->t_ck + 1;
228
229 spd->t_rfc = (buf->trfc_min_lsb | (buf->trfc_min_msb << 8)) * mtb /
230 1000;
231 spd->t_wtr = (buf->twtr_min * mtb) / spd->t_ck;
232 spd->t_rtp = (buf->trtp_min * mtb) / spd->t_ck;
233
234 spd->t_xs = (((spd->t_rfc + 10) * 1000) / spd->t_ck);
235 spd->t_rfc = ((spd->t_rfc * 1000) - 1) / spd->t_ck + 1;
236
237 spd->t_faw = (((buf->tfaw_msb << 8) | buf->tfaw_min) * mtb) / spd->t_ck;
238 spd->t_rrd2 = ((((buf->tfaw_msb << 8) |
239 buf->tfaw_min) * mtb) / (4 * spd->t_ck)) - 1;
240
241 /* Hard-coded values */
242 spd->t_mrd = 0x00;
243 spd->t_mod = 0x00;
244 spd->t_wlo = 0x0C;
245 spd->t_wlmrd = 0x28;
246 spd->t_xsdll = 0x200;
247 spd->t_ras_max = 0x0F;
248 spd->t_csta = 0x05;
249 spd->t_dllk = 0x200;
250
251 /* CAS Write Latency */
252 if (spd->t_ck >= 2500)
253 spd->cwl = 0;
254 else if (spd->t_ck >= 1875)
255 spd->cwl = 1;
256 else if (spd->t_ck >= 1500)
257 spd->cwl = 2;
258 else if (spd->t_ck >= 1250)
259 spd->cwl = 3;
260 else if (spd->t_ck >= 1071)
261 spd->cwl = 4;
262 else
263 spd->cwl = 5;
264
265 /* SD:RAM Thermal and Refresh Options */
266 spd->asr = (buf->therm_ref_opt & 0x04) >> 2;
267 spd->pasr = (buf->therm_ref_opt & 0x80) >> 7;
268 spd->t_zqcs = 64;
269
270 spd->t_refprd = (TEMP == NORMAL_TEMP) ? 7812500 : 3906250;
271 spd->t_refprd = spd->t_refprd / spd->t_ck;
272
273 spd->refresh_rate = spd->t_refprd;
274 spd->t_refprd = spd->t_refprd * 5;
275
276 /* Set MISC PHY space registers fields */
277 if ((clk_freq / 2) >= 166 && (clk_freq / 2 < 275))
278 spd->freqsel = 0x03;
279 else if ((clk_freq / 2) > 225 && (clk_freq / 2 < 385))
280 spd->freqsel = 0x01;
281 else if ((clk_freq / 2) > 335 && (clk_freq / 2 < 534))
282 spd->freqsel = 0x00;
283
284 spd->t_dinit0 = 500000000 / spd->t_ck; /* CKE low time 500 us */
285 spd->t_dinit1 = spd->t_xs;
286 spd->t_dinit2 = 200000000 / spd->t_ck; /* Reset low time 200 us */
287 /* Time from ZQ initialization command to first command (1 us) */
288 spd->t_dinit3 = 1000000 / spd->t_ck;
289
290 spd->t_pllgs = PLLGS_VAL + 1;
291 spd->t_pllpd = PLLPD_VAL + 1;
292 spd->t_plllock = PLLLOCK_VAL + 1;
293 spd->t_pllrst = PLLRST_VAL;
294 spd->t_phyrst = PHYRST_VAL;
295
296 spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024;
297
298 return 0;
299 }
300
init_ddr3param(struct ddr3_spd_cb * spd_cb,struct ddr3_sodimm * spd)301 static void init_ddr3param(struct ddr3_spd_cb *spd_cb,
302 struct ddr3_sodimm *spd)
303 {
304 spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13;
305 spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK);
306 spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23));
307 spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) |
308 ((spd->t_pllgs & 0x7fff) << 6) | (spd->t_phyrst & 0x3f);
309 spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) |
310 (spd->t_pllrst & 0x1fff);
311 spd_cb->phy_cfg.ptr2 = 0;
312 spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) |
313 (spd->t_dinit0 & 0xfffff);
314 spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) |
315 (spd->t_dinit2 & 0x3ffff);
316
317 spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK;
318 spd_cb->phy_cfg.dcr_val = 1 << 10;
319
320 if (spd->mirrored) {
321 spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK;
322 spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29);
323 }
324
325 spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 |
326 (spd->t_rrd & 0xf) << 22 |
327 (spd->t_ras & 0x3f) << 16 | (spd->t_rcd & 0xf) << 12 |
328 (spd->t_rp & 0xf) << 8 | (spd->t_wtr & 0xf) << 4 |
329 (spd->t_rtp & 0xf);
330 spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 |
331 (spd->t_wlmrd & 0x3f) << 20 | (spd->t_rfc & 0x1ff) << 11 |
332 (spd->t_faw & 0x3f) << 5 | (spd->t_mod & 0x7) << 2 |
333 (spd->t_mrd & 0x3);
334
335 spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 |
336 (spd->t_dllk & 0x3ff) << 19 | (spd->t_ckesr & 0xf) << 15;
337
338 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ?
339 spd->t_xp : spd->t_xpdll) &
340 0x1f) << 10;
341
342 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ?
343 spd->t_xs : spd->t_xsdll) &
344 0x3ff);
345
346 spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 |
347 0 << 7 | ((spd->cas & 0x0E) >> 1) << 4 | 0 << 3 |
348 (spd->cas & 0x01) << 2;
349
350 spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 |
351 ((DDR_TERM >> 2) & 1) << 9 | ((DDR_TERM >> 1) & 1) << 6 |
352 (DDR_TERM & 0x1) << 2 | ((SDRAM_DRIVE >> 1) & 1) << 5 |
353 (SDRAM_DRIVE & 1) << 1 | 0 << 0;
354
355 spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 |
356 (spd->cwl & 7) << 3 | (spd->pasr & 7);
357
358 spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7;
359 spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff);
360
361 spd_cb->phy_cfg.zq0cr1 = 0x0000005D;
362 spd_cb->phy_cfg.zq1cr1 = 0x0000005B;
363 spd_cb->phy_cfg.zq2cr1 = 0x0000005B;
364
365 spd_cb->phy_cfg.pir_v1 = 0x00000033;
366 spd_cb->phy_cfg.pir_v2 = 0x0000FF81;
367
368 /* EMIF Registers */
369 spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 |
370 (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 |
371 (spd->cas & 0xf) << 8 | (spd->ibank & 3) << 5 |
372 (spd->buswidth & 3) << 12 | (spd->pagesize & 3);
373
374 if (spd->rank == 2)
375 spd_cb->emif_cfg.sdcfg |= 1 << 3;
376
377 spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 |
378 ((spd->t_ras - 1) & 0x7f) << 18 |
379 ((spd->t_rc - 1) & 0xff) << 10 |
380 (spd->t_rrd2 & 0x3f) << 4 |
381 ((spd->t_wtr - 1) & 0xf);
382
383 spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 |
384 ((spd->t_rcd - 1) & 0x1f);
385
386 spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 |
387 ((spd->t_xs - 1) & 0x3ff) << 18 |
388 ((spd->t_xsdll - 1) & 0x3ff) << 8 |
389 ((spd->t_rtp - 1) & 0xf) << 4 | ((spd->t_cke) & 0xf);
390
391 spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 |
392 ((spd->t_ckesr - 1) & 0xf) << 24 |
393 ((spd->t_zqcs - 1) & 0xff) << 16 |
394 ((spd->t_rfc - 1) & 0x3ff) << 4 |
395 (spd->t_ras_max & 0xf);
396
397 spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff;
398
399 /* TODO zqcfg value fixed ,May be required correction for K2E evm. */
400 spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200;
401 }
402
ddr3_read_spd(ddr3_spd_eeprom_t * spd_params)403 static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
404 {
405 int ret;
406 #ifndef CONFIG_DM_I2C
407 int old_bus;
408
409 i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
410
411 old_bus = i2c_get_bus_num();
412 i2c_set_bus_num(1);
413
414 ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256);
415
416 i2c_set_bus_num(old_bus);
417 #else
418 struct udevice *dev;
419
420 ret = i2c_get_chip_for_busnum(1, 0x53, 1, &dev);
421 if (!ret)
422 ret = dm_i2c_read(dev, 0, (unsigned char *)spd_params, 256);
423 #endif
424 if (ret) {
425 printf("Cannot read DIMM params\n");
426 return 1;
427 }
428
429 if (ddr3_spd_check(spd_params))
430 return 1;
431
432 return 0;
433 }
434
ddr3_get_size(void)435 int ddr3_get_size(void)
436 {
437 ddr3_spd_eeprom_t spd_params;
438
439 if (ddr3_read_spd(&spd_params))
440 return 0;
441
442 return ddr3_get_size_in_mb(&spd_params) / 1024;
443 }
444
ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb * spd_cb)445 int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb)
446 {
447 struct ddr3_sodimm spd;
448 ddr3_spd_eeprom_t spd_params;
449
450 memset(&spd, 0, sizeof(spd));
451
452 if (ddr3_read_spd(&spd_params))
453 return 1;
454
455 if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) {
456 printf("Timing caclulation error\n");
457 return 1;
458 }
459
460 strncpy(spd_cb->dimm_name, (char *)spd_params.mpart, 18);
461 spd_cb->dimm_name[18] = '\0';
462
463 init_ddr3param(spd_cb, &spd);
464
465 dump_emif_config(&spd_cb->emif_cfg);
466 dump_phy_config(&spd_cb->phy_cfg);
467
468 return 0;
469 }
470