1 /* 2 * Keystone2: DDR3 initialization 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <asm/io.h> 11 #include <common.h> 12 #include <asm/arch/msmc.h> 13 #include <asm/arch/ddr3.h> 14 #include <asm/arch/psc_defs.h> 15 16 #include <asm/ti-common/ti-edma3.h> 17 18 #define DDR3_EDMA_BLK_SIZE_SHIFT 10 19 #define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT) 20 #define DDR3_EDMA_BCNT 0x8000 21 #define DDR3_EDMA_CCNT 1 22 #define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT) 23 #define DDR3_EDMA_SLOT_NUM 1 24 25 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) 26 { 27 unsigned int tmp; 28 29 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) 30 & 0x00000001) != 0x00000001) 31 ; 32 33 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); 34 35 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); 36 tmp &= ~(phy_cfg->pgcr1_mask); 37 tmp |= phy_cfg->pgcr1_val; 38 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); 39 40 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); 41 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); 42 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); 43 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); 44 45 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); 46 tmp &= ~(phy_cfg->dcr_mask); 47 tmp |= phy_cfg->dcr_val; 48 __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); 49 50 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); 51 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); 52 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); 53 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); 54 __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); 55 if (!cpu_is_k2g()) 56 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); 57 __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); 58 __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); 59 60 __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); 61 __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET); 62 __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET); 63 64 __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET); 65 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) 66 ; 67 68 if (cpu_is_k2g()) { 69 setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); 70 clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); 71 clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); 72 clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1); 73 clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1); 74 } 75 76 __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); 77 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) 78 ; 79 } 80 81 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) 82 { 83 __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); 84 __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); 85 __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET); 86 __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET); 87 __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET); 88 __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); 89 __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); 90 } 91 92 int ddr3_ecc_support_rmw(u32 base) 93 { 94 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); 95 96 /* Check the DDR3 controller ID reg if the controllers 97 supports ECC RMW or not */ 98 if (value == 0x40461C02) 99 return 1; 100 101 return 0; 102 } 103 104 static void ddr3_ecc_config(u32 base, u32 value) 105 { 106 u32 data; 107 108 __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET); 109 udelay(100000); /* delay required to synchronize across clock domains */ 110 111 if (value & KS2_DDR3_ECC_EN) { 112 /* Clear the 1-bit error count */ 113 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 114 __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 115 116 /* enable the ECC interrupt */ 117 __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | 118 KS2_DDR3_WR_ECC_ERR_SYS, 119 base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET); 120 121 /* Clear the ECC error interrupt status */ 122 __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | 123 KS2_DDR3_WR_ECC_ERR_SYS, 124 base + KS2_DDR3_ECC_INT_STATUS_OFFSET); 125 } 126 } 127 128 static void ddr3_reset_data(u32 base, u32 ddr3_size) 129 { 130 u32 mpax[2]; 131 u32 seg_num; 132 u32 seg, blks, dst, edma_blks; 133 struct edma3_slot_config slot; 134 struct edma3_channel_config edma_channel; 135 u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, }; 136 137 /* Setup an edma to copy the 1k block to the entire DDR */ 138 puts("\nClear entire DDR3 memory to enable ECC\n"); 139 140 /* save the SES MPAX regs */ 141 msmc_get_ses_mpax(8, 0, mpax); 142 143 /* setup edma slot 1 configuration */ 144 slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB | 145 EDMA3_SLOPT_COMP_CODE(0) | 146 EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC; 147 slot.bcnt = DDR3_EDMA_BCNT; 148 slot.acnt = DDR3_EDMA_BLK_SIZE; 149 slot.ccnt = DDR3_EDMA_CCNT; 150 slot.src_bidx = 0; 151 slot.dst_bidx = DDR3_EDMA_BLK_SIZE; 152 slot.src_cidx = 0; 153 slot.dst_cidx = 0; 154 slot.link = EDMA3_PARSET_NULL_LINK; 155 slot.bcntrld = 0; 156 edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot); 157 158 /* configure quik edma channel */ 159 edma_channel.slot = DDR3_EDMA_SLOT_NUM; 160 edma_channel.chnum = 0; 161 edma_channel.complete_code = 0; 162 /* event trigger after dst update */ 163 edma_channel.trigger_slot_word = EDMA3_TWORD(dst); 164 qedma3_start(KS2_EDMA0_BASE, &edma_channel); 165 166 /* DDR3 size in segments (4KB seg size) */ 167 seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT); 168 169 for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) { 170 /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF 171 access slave interface so that edma driver can access */ 172 msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT, 173 KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G); 174 175 if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM) 176 edma_blks = KS2_MSMC_MAP_SEG_NUM << 177 (KS2_MSMC_SEG_SIZE_SHIFT 178 - DDR3_EDMA_BLK_SIZE_SHIFT); 179 else 180 edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT 181 - DDR3_EDMA_BLK_SIZE_SHIFT); 182 183 /* Use edma driver to scrub 2GB DDR memory */ 184 for (dst = base, blks = 0; blks < edma_blks; 185 blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) { 186 edma3_set_src_addr(KS2_EDMA0_BASE, 187 edma_channel.slot, (u32)edma_src); 188 edma3_set_dest_addr(KS2_EDMA0_BASE, 189 edma_channel.slot, (u32)dst); 190 191 while (edma3_check_for_transfer(KS2_EDMA0_BASE, 192 &edma_channel)) 193 udelay(10); 194 } 195 } 196 197 qedma3_stop(KS2_EDMA0_BASE, &edma_channel); 198 199 /* restore the SES MPAX regs */ 200 msmc_set_ses_mpax(8, 0, mpax); 201 } 202 203 static void ddr3_ecc_init_range(u32 base) 204 { 205 u32 ecc_val = KS2_DDR3_ECC_EN; 206 u32 rmw = ddr3_ecc_support_rmw(base); 207 208 if (rmw) 209 ecc_val |= KS2_DDR3_ECC_RMW_EN; 210 211 __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); 212 213 ddr3_ecc_config(base, ecc_val); 214 } 215 216 void ddr3_enable_ecc(u32 base, int test) 217 { 218 u32 ecc_val = KS2_DDR3_ECC_ENABLE; 219 u32 rmw = ddr3_ecc_support_rmw(base); 220 221 if (test) 222 ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN; 223 224 if (!rmw) { 225 if (!test) 226 /* by default, disable ecc when rmw = 0 and no 227 ecc test */ 228 ecc_val = 0; 229 } else { 230 ecc_val |= KS2_DDR3_ECC_RMW_EN; 231 } 232 233 ddr3_ecc_config(base, ecc_val); 234 } 235 236 void ddr3_disable_ecc(u32 base) 237 { 238 ddr3_ecc_config(base, 0); 239 } 240 241 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) 242 static void cic_init(u32 base) 243 { 244 /* Disable CIC global interrupts */ 245 __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE); 246 247 /* Set to normal mode, no nesting, no priority hold */ 248 __raw_writel(0, base + KS2_CIC_CTRL); 249 __raw_writel(0, base + KS2_CIC_HOST_CTRL); 250 251 /* Enable CIC global interrupts */ 252 __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE); 253 } 254 255 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) 256 { 257 /* Map the system interrupt to a CIC channel */ 258 __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num); 259 260 /* Enable CIC system interrupt */ 261 __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET); 262 263 /* Enable CIC Host interrupt */ 264 __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET); 265 } 266 267 static void ddr3_map_ecc_cic2_irq(u32 base) 268 { 269 cic_init(base); 270 cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM, 271 KS2_CIC2_DDR3_ECC_IRQ_NUM); 272 } 273 #endif 274 275 void ddr3_init_ecc(u32 base, u32 ddr3_size) 276 { 277 if (!ddr3_ecc_support_rmw(base)) { 278 ddr3_disable_ecc(base); 279 return; 280 } 281 282 ddr3_ecc_init_range(base); 283 ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); 284 285 /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ 286 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) 287 ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE); 288 #endif 289 ddr3_enable_ecc(base, 0); 290 } 291 292 void ddr3_check_ecc_int(u32 base) 293 { 294 char *env; 295 int ecc_test = 0; 296 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); 297 298 env = getenv("ecc_test"); 299 if (env) 300 ecc_test = simple_strtol(env, NULL, 0); 301 302 if (value & KS2_DDR3_WR_ECC_ERR_SYS) 303 puts("DDR3 ECC write error interrupted\n"); 304 305 if (value & KS2_DDR3_2B_ECC_ERR_SYS) { 306 puts("DDR3 ECC 2-bit error interrupted\n"); 307 308 if (!ecc_test) { 309 puts("Reseting the device ...\n"); 310 reset_cpu(0); 311 } 312 } 313 314 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 315 if (value) { 316 printf("1-bit ECC err count: 0x%x\n", value); 317 value = __raw_readl(base + 318 KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET); 319 printf("1-bit ECC err address log: 0x%x\n", value); 320 } 321 } 322 323 void ddr3_reset_ddrphy(void) 324 { 325 u32 tmp; 326 327 /* Assert DDR3A PHY reset */ 328 tmp = readl(KS2_DDR3APLLCTL1); 329 tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; 330 writel(tmp, KS2_DDR3APLLCTL1); 331 332 /* wait 10us to catch the reset */ 333 udelay(10); 334 335 /* Release DDR3A PHY reset */ 336 tmp = readl(KS2_DDR3APLLCTL1); 337 tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; 338 __raw_writel(tmp, KS2_DDR3APLLCTL1); 339 } 340 341 #ifdef CONFIG_SOC_K2HK 342 /** 343 * ddr3_reset_workaround - reset workaround in case if leveling error 344 * detected for PG 1.0 and 1.1 k2hk SoCs 345 */ 346 void ddr3_err_reset_workaround(void) 347 { 348 unsigned int tmp; 349 unsigned int tmp_a; 350 unsigned int tmp_b; 351 352 /* 353 * Check for PGSR0 error bits of DDR3 PHY. 354 * Check for WLERR, QSGERR, WLAERR, 355 * RDERR, WDERR, REERR, WEERR error to see if they are set or not 356 */ 357 tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); 358 tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); 359 360 if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) { 361 printf("DDR Leveling Error Detected!\n"); 362 printf("DDR3A PGSR0 = 0x%x\n", tmp_a); 363 printf("DDR3B PGSR0 = 0x%x\n", tmp_b); 364 365 /* 366 * Write Keys to KICK registers to enable writes to registers 367 * in boot config space 368 */ 369 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); 370 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); 371 372 /* 373 * Move DDR3A Module out of reset isolation by setting 374 * MDCTL23[12] = 0 375 */ 376 tmp_a = __raw_readl(KS2_PSC_BASE + 377 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); 378 379 tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0); 380 __raw_writel(tmp_a, KS2_PSC_BASE + 381 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); 382 383 /* 384 * Move DDR3B Module out of reset isolation by setting 385 * MDCTL24[12] = 0 386 */ 387 tmp_b = __raw_readl(KS2_PSC_BASE + 388 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); 389 tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0); 390 __raw_writel(tmp_b, KS2_PSC_BASE + 391 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); 392 393 /* 394 * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes 395 * to RSTCTRL and RSTCFG 396 */ 397 tmp = __raw_readl(KS2_RSTCTRL); 398 tmp &= KS2_RSTCTRL_MASK; 399 tmp |= KS2_RSTCTRL_KEY; 400 __raw_writel(tmp, KS2_RSTCTRL); 401 402 /* 403 * Set PLL Controller to drive hard reset on SW trigger by 404 * setting RSTCFG[13] = 0 405 */ 406 tmp = __raw_readl(KS2_RSTCTRL_RSCFG); 407 tmp &= ~KS2_RSTYPE_PLL_SOFT; 408 __raw_writel(tmp, KS2_RSTCTRL_RSCFG); 409 410 reset_cpu(0); 411 } 412 } 413 #endif 414