1 /* 2 * Keystone2: DDR3 initialization 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <asm/io.h> 11 #include <common.h> 12 #include <asm/arch/msmc.h> 13 #include <asm/arch/ddr3.h> 14 #include <asm/arch/psc_defs.h> 15 16 #include <asm/ti-common/ti-edma3.h> 17 18 #define DDR3_EDMA_BLK_SIZE_SHIFT 10 19 #define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT) 20 #define DDR3_EDMA_BCNT 0x8000 21 #define DDR3_EDMA_CCNT 1 22 #define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT) 23 #define DDR3_EDMA_SLOT_NUM 1 24 25 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) 26 { 27 unsigned int tmp; 28 29 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) 30 & 0x00000001) != 0x00000001) 31 ; 32 33 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); 34 35 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); 36 tmp &= ~(phy_cfg->pgcr1_mask); 37 tmp |= phy_cfg->pgcr1_val; 38 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); 39 40 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); 41 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); 42 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); 43 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); 44 45 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); 46 tmp &= ~(phy_cfg->dcr_mask); 47 tmp |= phy_cfg->dcr_val; 48 __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); 49 50 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); 51 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); 52 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); 53 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); 54 __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); 55 if (!cpu_is_k2g()) 56 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); 57 __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); 58 __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); 59 60 __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); 61 __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET); 62 __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET); 63 64 __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET); 65 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) 66 ; 67 68 /* Disable ECC for K2G */ 69 if (cpu_is_k2g()) { 70 clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); 71 clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); 72 clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); 73 clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1); 74 clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1); 75 } 76 77 __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); 78 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) 79 ; 80 } 81 82 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) 83 { 84 __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); 85 __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); 86 __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET); 87 __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET); 88 __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET); 89 __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); 90 __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); 91 } 92 93 int ddr3_ecc_support_rmw(u32 base) 94 { 95 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); 96 97 /* Check the DDR3 controller ID reg if the controllers 98 supports ECC RMW or not */ 99 if (value == 0x40461C02) 100 return 1; 101 102 return 0; 103 } 104 105 static void ddr3_ecc_config(u32 base, u32 value) 106 { 107 u32 data; 108 109 __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET); 110 udelay(100000); /* delay required to synchronize across clock domains */ 111 112 if (value & KS2_DDR3_ECC_EN) { 113 /* Clear the 1-bit error count */ 114 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 115 __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 116 117 /* enable the ECC interrupt */ 118 __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | 119 KS2_DDR3_WR_ECC_ERR_SYS, 120 base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET); 121 122 /* Clear the ECC error interrupt status */ 123 __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | 124 KS2_DDR3_WR_ECC_ERR_SYS, 125 base + KS2_DDR3_ECC_INT_STATUS_OFFSET); 126 } 127 } 128 129 static void ddr3_reset_data(u32 base, u32 ddr3_size) 130 { 131 u32 mpax[2]; 132 u32 seg_num; 133 u32 seg, blks, dst, edma_blks; 134 struct edma3_slot_config slot; 135 struct edma3_channel_config edma_channel; 136 u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, }; 137 138 /* Setup an edma to copy the 1k block to the entire DDR */ 139 puts("\nClear entire DDR3 memory to enable ECC\n"); 140 141 /* save the SES MPAX regs */ 142 msmc_get_ses_mpax(8, 0, mpax); 143 144 /* setup edma slot 1 configuration */ 145 slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB | 146 EDMA3_SLOPT_COMP_CODE(0) | 147 EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC; 148 slot.bcnt = DDR3_EDMA_BCNT; 149 slot.acnt = DDR3_EDMA_BLK_SIZE; 150 slot.ccnt = DDR3_EDMA_CCNT; 151 slot.src_bidx = 0; 152 slot.dst_bidx = DDR3_EDMA_BLK_SIZE; 153 slot.src_cidx = 0; 154 slot.dst_cidx = 0; 155 slot.link = EDMA3_PARSET_NULL_LINK; 156 slot.bcntrld = 0; 157 edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot); 158 159 /* configure quik edma channel */ 160 edma_channel.slot = DDR3_EDMA_SLOT_NUM; 161 edma_channel.chnum = 0; 162 edma_channel.complete_code = 0; 163 /* event trigger after dst update */ 164 edma_channel.trigger_slot_word = EDMA3_TWORD(dst); 165 qedma3_start(KS2_EDMA0_BASE, &edma_channel); 166 167 /* DDR3 size in segments (4KB seg size) */ 168 seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT); 169 170 for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) { 171 /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF 172 access slave interface so that edma driver can access */ 173 msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT, 174 KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G); 175 176 if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM) 177 edma_blks = KS2_MSMC_MAP_SEG_NUM << 178 (KS2_MSMC_SEG_SIZE_SHIFT 179 - DDR3_EDMA_BLK_SIZE_SHIFT); 180 else 181 edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT 182 - DDR3_EDMA_BLK_SIZE_SHIFT); 183 184 /* Use edma driver to scrub 2GB DDR memory */ 185 for (dst = base, blks = 0; blks < edma_blks; 186 blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) { 187 edma3_set_src_addr(KS2_EDMA0_BASE, 188 edma_channel.slot, (u32)edma_src); 189 edma3_set_dest_addr(KS2_EDMA0_BASE, 190 edma_channel.slot, (u32)dst); 191 192 while (edma3_check_for_transfer(KS2_EDMA0_BASE, 193 &edma_channel)) 194 udelay(10); 195 } 196 } 197 198 qedma3_stop(KS2_EDMA0_BASE, &edma_channel); 199 200 /* restore the SES MPAX regs */ 201 msmc_set_ses_mpax(8, 0, mpax); 202 } 203 204 static void ddr3_ecc_init_range(u32 base) 205 { 206 u32 ecc_val = KS2_DDR3_ECC_EN; 207 u32 rmw = ddr3_ecc_support_rmw(base); 208 209 if (rmw) 210 ecc_val |= KS2_DDR3_ECC_RMW_EN; 211 212 __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); 213 214 ddr3_ecc_config(base, ecc_val); 215 } 216 217 void ddr3_enable_ecc(u32 base, int test) 218 { 219 u32 ecc_val = KS2_DDR3_ECC_ENABLE; 220 u32 rmw = ddr3_ecc_support_rmw(base); 221 222 if (test) 223 ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN; 224 225 if (!rmw) { 226 if (!test) 227 /* by default, disable ecc when rmw = 0 and no 228 ecc test */ 229 ecc_val = 0; 230 } else { 231 ecc_val |= KS2_DDR3_ECC_RMW_EN; 232 } 233 234 ddr3_ecc_config(base, ecc_val); 235 } 236 237 void ddr3_disable_ecc(u32 base) 238 { 239 ddr3_ecc_config(base, 0); 240 } 241 242 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) 243 static void cic_init(u32 base) 244 { 245 /* Disable CIC global interrupts */ 246 __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE); 247 248 /* Set to normal mode, no nesting, no priority hold */ 249 __raw_writel(0, base + KS2_CIC_CTRL); 250 __raw_writel(0, base + KS2_CIC_HOST_CTRL); 251 252 /* Enable CIC global interrupts */ 253 __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE); 254 } 255 256 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) 257 { 258 /* Map the system interrupt to a CIC channel */ 259 __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num); 260 261 /* Enable CIC system interrupt */ 262 __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET); 263 264 /* Enable CIC Host interrupt */ 265 __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET); 266 } 267 268 static void ddr3_map_ecc_cic2_irq(u32 base) 269 { 270 cic_init(base); 271 cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM, 272 KS2_CIC2_DDR3_ECC_IRQ_NUM); 273 } 274 #endif 275 276 void ddr3_init_ecc(u32 base, u32 ddr3_size) 277 { 278 if (!ddr3_ecc_support_rmw(base)) { 279 ddr3_disable_ecc(base); 280 return; 281 } 282 283 ddr3_ecc_init_range(base); 284 ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); 285 286 /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ 287 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) 288 ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE); 289 #endif 290 ddr3_enable_ecc(base, 0); 291 } 292 293 void ddr3_check_ecc_int(u32 base) 294 { 295 char *env; 296 int ecc_test = 0; 297 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); 298 299 env = getenv("ecc_test"); 300 if (env) 301 ecc_test = simple_strtol(env, NULL, 0); 302 303 if (value & KS2_DDR3_WR_ECC_ERR_SYS) 304 puts("DDR3 ECC write error interrupted\n"); 305 306 if (value & KS2_DDR3_2B_ECC_ERR_SYS) { 307 puts("DDR3 ECC 2-bit error interrupted\n"); 308 309 if (!ecc_test) { 310 puts("Reseting the device ...\n"); 311 reset_cpu(0); 312 } 313 } 314 315 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); 316 if (value) { 317 printf("1-bit ECC err count: 0x%x\n", value); 318 value = __raw_readl(base + 319 KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET); 320 printf("1-bit ECC err address log: 0x%x\n", value); 321 } 322 } 323 324 void ddr3_reset_ddrphy(void) 325 { 326 u32 tmp; 327 328 /* Assert DDR3A PHY reset */ 329 tmp = readl(KS2_DDR3APLLCTL1); 330 tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; 331 writel(tmp, KS2_DDR3APLLCTL1); 332 333 /* wait 10us to catch the reset */ 334 udelay(10); 335 336 /* Release DDR3A PHY reset */ 337 tmp = readl(KS2_DDR3APLLCTL1); 338 tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; 339 __raw_writel(tmp, KS2_DDR3APLLCTL1); 340 } 341 342 #ifdef CONFIG_SOC_K2HK 343 /** 344 * ddr3_reset_workaround - reset workaround in case if leveling error 345 * detected for PG 1.0 and 1.1 k2hk SoCs 346 */ 347 void ddr3_err_reset_workaround(void) 348 { 349 unsigned int tmp; 350 unsigned int tmp_a; 351 unsigned int tmp_b; 352 353 /* 354 * Check for PGSR0 error bits of DDR3 PHY. 355 * Check for WLERR, QSGERR, WLAERR, 356 * RDERR, WDERR, REERR, WEERR error to see if they are set or not 357 */ 358 tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); 359 tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); 360 361 if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) { 362 printf("DDR Leveling Error Detected!\n"); 363 printf("DDR3A PGSR0 = 0x%x\n", tmp_a); 364 printf("DDR3B PGSR0 = 0x%x\n", tmp_b); 365 366 /* 367 * Write Keys to KICK registers to enable writes to registers 368 * in boot config space 369 */ 370 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); 371 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); 372 373 /* 374 * Move DDR3A Module out of reset isolation by setting 375 * MDCTL23[12] = 0 376 */ 377 tmp_a = __raw_readl(KS2_PSC_BASE + 378 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); 379 380 tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0); 381 __raw_writel(tmp_a, KS2_PSC_BASE + 382 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); 383 384 /* 385 * Move DDR3B Module out of reset isolation by setting 386 * MDCTL24[12] = 0 387 */ 388 tmp_b = __raw_readl(KS2_PSC_BASE + 389 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); 390 tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0); 391 __raw_writel(tmp_b, KS2_PSC_BASE + 392 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); 393 394 /* 395 * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes 396 * to RSTCTRL and RSTCFG 397 */ 398 tmp = __raw_readl(KS2_RSTCTRL); 399 tmp &= KS2_RSTCTRL_MASK; 400 tmp |= KS2_RSTCTRL_KEY; 401 __raw_writel(tmp, KS2_RSTCTRL); 402 403 /* 404 * Set PLL Controller to drive hard reset on SW trigger by 405 * setting RSTCFG[13] = 0 406 */ 407 tmp = __raw_readl(KS2_RSTCTRL_RSCFG); 408 tmp &= ~KS2_RSTYPE_PLL_SOFT; 409 __raw_writel(tmp, KS2_RSTCTRL_RSCFG); 410 411 reset_cpu(0); 412 } 413 } 414 #endif 415