1 /* 2 * Keystone2: pll initialization 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/clock_defs.h> 13 14 /* DEV and ARM speed definitions as specified in DEVSPEED register */ 15 int __weak speeds[DEVSPEED_NUMSPDS] = { 16 SPD1000, 17 SPD1200, 18 SPD1350, 19 SPD1400, 20 SPD1500, 21 SPD1400, 22 SPD1350, 23 SPD1200, 24 SPD1000, 25 SPD800, 26 }; 27 28 const struct keystone_pll_regs keystone_pll_regs[] = { 29 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, 30 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, 31 [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, 32 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, 33 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, 34 [UART_PLL] = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1}, 35 }; 36 37 inline void pll_pa_clk_sel(void) 38 { 39 setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK); 40 } 41 42 static void wait_for_completion(const struct pll_init_data *data) 43 { 44 int i; 45 for (i = 0; i < 100; i++) { 46 sdelay(450); 47 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) 48 break; 49 } 50 } 51 52 static inline void bypass_main_pll(const struct pll_init_data *data) 53 { 54 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | 55 PLLCTL_PLLEN_MASK); 56 57 /* 4 cycles of reference clock CLKIN*/ 58 sdelay(340); 59 } 60 61 static void configure_mult_div(const struct pll_init_data *data) 62 { 63 u32 pllm, plld, bwadj; 64 65 pllm = data->pll_m - 1; 66 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK; 67 68 /* Program Multiplier */ 69 if (data->pll == MAIN_PLL) 70 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); 71 72 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 73 CFG_PLLCTL0_PLLM_MASK, 74 pllm << CFG_PLLCTL0_PLLM_SHIFT); 75 76 /* Program BWADJ */ 77 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ 78 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 79 CFG_PLLCTL0_BWADJ_MASK, 80 (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) & 81 CFG_PLLCTL0_BWADJ_MASK); 82 bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS; 83 clrsetbits_le32(keystone_pll_regs[data->pll].reg1, 84 CFG_PLLCTL1_BWADJ_MASK, bwadj); 85 86 /* Program Divider */ 87 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 88 CFG_PLLCTL0_PLLD_MASK, plld); 89 } 90 91 void configure_main_pll(const struct pll_init_data *data) 92 { 93 u32 tmp, pllod, i, alnctl_val = 0; 94 u32 *offset; 95 96 pllod = data->pll_od - 1; 97 98 /* 100 micro sec for stabilization */ 99 sdelay(210000); 100 101 tmp = pllctl_reg_read(data->pll, secctl); 102 103 /* Check for Bypass */ 104 if (tmp & SECCTL_BYPASS_MASK) { 105 setbits_le32(keystone_pll_regs[data->pll].reg1, 106 CFG_PLLCTL1_ENSAT_MASK); 107 108 bypass_main_pll(data); 109 110 /* Powerdown and powerup Main Pll */ 111 pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK); 112 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); 113 /* 5 micro sec */ 114 sdelay(21000); 115 116 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); 117 } else { 118 bypass_main_pll(data); 119 } 120 121 configure_mult_div(data); 122 123 /* Program Output Divider */ 124 pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK, 125 ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK)); 126 127 /* Program PLLDIVn */ 128 wait_for_completion(data); 129 for (i = 0; i < PLLDIV_MAX; i++) { 130 if (i < 3) 131 offset = pllctl_reg(data->pll, div1) + i; 132 else 133 offset = pllctl_reg(data->pll, div4) + (i - 3); 134 135 if (divn_val[i] != -1) { 136 __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset); 137 alnctl_val |= BIT(i); 138 } 139 } 140 141 if (alnctl_val) { 142 pllctl_reg_setbits(data->pll, alnctl, alnctl_val); 143 /* 144 * Set GOSET bit in PLLCMD to initiate the GO operation 145 * to change the divide 146 */ 147 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK); 148 wait_for_completion(data); 149 } 150 151 /* Reset PLL */ 152 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK); 153 sdelay(21000); /* Wait for a minimum of 7 us*/ 154 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK); 155 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ 156 157 /* Enable PLL */ 158 pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK); 159 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK); 160 } 161 162 void configure_secondary_pll(const struct pll_init_data *data) 163 { 164 int pllod = data->pll_od - 1; 165 166 /* Enable Bypass mode */ 167 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK); 168 setbits_le32(keystone_pll_regs[data->pll].reg0, 169 CFG_PLLCTL0_BYPASS_MASK); 170 171 /* Enable Glitch free bypass for ARM PLL */ 172 if (cpu_is_k2hk() && data->pll == TETRIS_PLL) 173 clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); 174 175 configure_mult_div(data); 176 177 /* Program Output Divider */ 178 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 179 CFG_PLLCTL0_CLKOD_MASK, 180 (pllod << CFG_PLLCTL0_CLKOD_SHIFT) & 181 CFG_PLLCTL0_CLKOD_MASK); 182 183 /* Reset PLL */ 184 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); 185 /* Wait for 5 micro seconds */ 186 sdelay(21000); 187 188 /* Select the Output of PASS PLL as input to PASS */ 189 if (data->pll == PASS_PLL && cpu_is_k2hk()) 190 pll_pa_clk_sel(); 191 192 /* Select the Output of ARM PLL as input to ARM */ 193 if (data->pll == TETRIS_PLL) 194 setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); 195 196 clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); 197 /* Wait for 500 * REFCLK cucles * (PLLD + 1) */ 198 sdelay(105000); 199 200 /* Switch to PLL mode */ 201 clrbits_le32(keystone_pll_regs[data->pll].reg0, 202 CFG_PLLCTL0_BYPASS_MASK); 203 } 204 205 void init_pll(const struct pll_init_data *data) 206 { 207 if (data->pll == MAIN_PLL) 208 configure_main_pll(data); 209 else 210 configure_secondary_pll(data); 211 212 /* 213 * This is required to provide a delay between multiple 214 * consequent PPL configurations 215 */ 216 sdelay(210000); 217 } 218 219 void init_plls(void) 220 { 221 struct pll_init_data *data; 222 int pll; 223 224 for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) { 225 data = get_pll_init_data(pll); 226 if (data) 227 init_pll(data); 228 } 229 } 230 231 static int get_max_speed(u32 val, u32 speed_supported) 232 { 233 int speed; 234 235 /* Left most setbit gives the speed */ 236 for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) { 237 if ((val & BIT(speed)) & speed_supported) 238 return speeds[speed]; 239 } 240 241 /* If no bit is set, use SPD800 */ 242 return SPD800; 243 } 244 245 static inline u32 read_efuse_bootrom(void) 246 { 247 if (cpu_is_k2hk() && (cpu_revision() <= 1)) 248 return __raw_readl(KS2_REV1_DEVSPEED); 249 else 250 return __raw_readl(KS2_EFUSE_BOOTROM); 251 } 252 253 int get_max_arm_speed(void) 254 { 255 u32 armspeed = read_efuse_bootrom(); 256 257 armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >> 258 DEVSPEED_ARMSPEED_SHIFT; 259 260 return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS); 261 } 262 263 int get_max_dev_speed(void) 264 { 265 u32 devspeed = read_efuse_bootrom(); 266 267 devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >> 268 DEVSPEED_DEVSPEED_SHIFT; 269 270 return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS); 271 } 272 273 /** 274 * pll_freq_get - get pll frequency 275 * @pll: pll identifier 276 */ 277 static unsigned long pll_freq_get(int pll) 278 { 279 unsigned long mult = 1, prediv = 1, output_div = 2; 280 unsigned long ret; 281 u32 tmp, reg; 282 283 if (pll == MAIN_PLL) { 284 ret = external_clk[sys_clk]; 285 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) { 286 /* PLL mode */ 287 tmp = __raw_readl(KS2_MAINPLLCTL0); 288 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; 289 mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >> 290 CFG_PLLCTL0_PLLM_SHIFT | 291 (pllctl_reg_read(pll, mult) & 292 PLLM_MULT_LO_MASK)) + 1; 293 output_div = ((pllctl_reg_read(pll, secctl) & 294 SECCTL_OP_DIV_MASK) >> 295 SECCTL_OP_DIV_SHIFT) + 1; 296 297 ret = ret / prediv / output_div * mult; 298 } 299 } else { 300 switch (pll) { 301 case PASS_PLL: 302 ret = external_clk[pa_clk]; 303 reg = KS2_PASSPLLCTL0; 304 break; 305 case TETRIS_PLL: 306 ret = external_clk[tetris_clk]; 307 reg = KS2_ARMPLLCTL0; 308 break; 309 case DDR3A_PLL: 310 ret = external_clk[ddr3a_clk]; 311 reg = KS2_DDR3APLLCTL0; 312 break; 313 case DDR3B_PLL: 314 ret = external_clk[ddr3b_clk]; 315 reg = KS2_DDR3BPLLCTL0; 316 break; 317 case UART_PLL: 318 ret = external_clk[uart_clk]; 319 reg = KS2_UARTPLLCTL0; 320 break; 321 default: 322 return 0; 323 } 324 325 tmp = __raw_readl(reg); 326 327 if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) { 328 /* Bypass disabled */ 329 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; 330 mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >> 331 CFG_PLLCTL0_PLLM_SHIFT) + 1; 332 output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >> 333 CFG_PLLCTL0_CLKOD_SHIFT) + 1; 334 ret = ((ret / prediv) * mult) / output_div; 335 } 336 } 337 338 return ret; 339 } 340 341 unsigned long clk_get_rate(unsigned int clk) 342 { 343 unsigned long freq = 0; 344 345 switch (clk) { 346 case core_pll_clk: 347 freq = pll_freq_get(CORE_PLL); 348 break; 349 case pass_pll_clk: 350 freq = pll_freq_get(PASS_PLL); 351 break; 352 case tetris_pll_clk: 353 if (!cpu_is_k2e()) 354 freq = pll_freq_get(TETRIS_PLL); 355 break; 356 case ddr3a_pll_clk: 357 freq = pll_freq_get(DDR3A_PLL); 358 break; 359 case ddr3b_pll_clk: 360 if (cpu_is_k2hk()) 361 freq = pll_freq_get(DDR3B_PLL); 362 break; 363 case uart_pll_clk: 364 if (cpu_is_k2g()) 365 freq = pll_freq_get(UART_PLL); 366 break; 367 case sys_clk0_1_clk: 368 case sys_clk0_clk: 369 freq = pll_freq_get(CORE_PLL) / pll0div_read(1); 370 break; 371 case sys_clk1_clk: 372 return pll_freq_get(CORE_PLL) / pll0div_read(2); 373 break; 374 case sys_clk2_clk: 375 freq = pll_freq_get(CORE_PLL) / pll0div_read(3); 376 break; 377 case sys_clk3_clk: 378 freq = pll_freq_get(CORE_PLL) / pll0div_read(4); 379 break; 380 case sys_clk0_2_clk: 381 freq = clk_get_rate(sys_clk0_clk) / 2; 382 break; 383 case sys_clk0_3_clk: 384 freq = clk_get_rate(sys_clk0_clk) / 3; 385 break; 386 case sys_clk0_4_clk: 387 freq = clk_get_rate(sys_clk0_clk) / 4; 388 break; 389 case sys_clk0_6_clk: 390 freq = clk_get_rate(sys_clk0_clk) / 6; 391 break; 392 case sys_clk0_8_clk: 393 freq = clk_get_rate(sys_clk0_clk) / 8; 394 break; 395 case sys_clk0_12_clk: 396 freq = clk_get_rate(sys_clk0_clk) / 12; 397 break; 398 case sys_clk0_24_clk: 399 freq = clk_get_rate(sys_clk0_clk) / 24; 400 break; 401 case sys_clk1_3_clk: 402 freq = clk_get_rate(sys_clk1_clk) / 3; 403 break; 404 case sys_clk1_4_clk: 405 freq = clk_get_rate(sys_clk1_clk) / 4; 406 break; 407 case sys_clk1_6_clk: 408 freq = clk_get_rate(sys_clk1_clk) / 6; 409 break; 410 case sys_clk1_12_clk: 411 freq = clk_get_rate(sys_clk1_clk) / 12; 412 break; 413 default: 414 break; 415 } 416 417 return freq; 418 } 419