1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/mach-imx/boot_mode.h> 13 #include <asm/mach-imx/dma.h> 14 #include <asm/mach-imx/hab.h> 15 #include <asm/mach-imx/rdc-sema.h> 16 #include <asm/arch/imx-rdc.h> 17 #include <asm/arch/crm_regs.h> 18 #include <dm.h> 19 #include <imx_thermal.h> 20 #include <fsl_sec.h> 21 #include <asm/setup.h> 22 23 #if defined(CONFIG_IMX_THERMAL) 24 static const struct imx_thermal_plat imx7_thermal_plat = { 25 .regs = (void *)ANATOP_BASE_ADDR, 26 .fuse_bank = 3, 27 .fuse_word = 3, 28 }; 29 30 U_BOOT_DEVICE(imx7_thermal) = { 31 .name = "imx_thermal", 32 .platdata = &imx7_thermal_plat, 33 }; 34 #endif 35 36 #if CONFIG_IS_ENABLED(IMX_RDC) 37 /* 38 * In current design, if any peripheral was assigned to both A7 and M4, 39 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter 40 * low power mode. So M4 sleep will cause some peripherals fail to work 41 * at A7 core side. At default, all resources are in domain 0 - 3. 42 * 43 * There are 26 peripherals impacted by this IC issue: 44 * SIM2(sim2/emvsim2) 45 * SIM1(sim1/emvsim1) 46 * UART1/UART2/UART3/UART4/UART5/UART6/UART7 47 * SAI1/SAI2/SAI3 48 * WDOG1/WDOG2/WDOG3/WDOG4 49 * GPT1/GPT2/GPT3/GPT4 50 * PWM1/PWM2/PWM3/PWM4 51 * ENET1/ENET2 52 * Software Workaround: 53 * Here we setup some resources to domain 0 where M4 codes will move 54 * the M4 out of this domain. Then M4 is not able to access them any longer. 55 * This is a workaround for ic issue. So the peripherals are not shared 56 * by them. This way requires the uboot implemented the RDC driver and 57 * set the 26 IPs above to domain 0 only. M4 code will assign resource 58 * to its own domain, if it want to use the resource. 59 */ 60 static rdc_peri_cfg_t const resources[] = { 61 (RDC_PER_SIM1 | RDC_DOMAIN(0)), 62 (RDC_PER_SIM2 | RDC_DOMAIN(0)), 63 (RDC_PER_UART1 | RDC_DOMAIN(0)), 64 (RDC_PER_UART2 | RDC_DOMAIN(0)), 65 (RDC_PER_UART3 | RDC_DOMAIN(0)), 66 (RDC_PER_UART4 | RDC_DOMAIN(0)), 67 (RDC_PER_UART5 | RDC_DOMAIN(0)), 68 (RDC_PER_UART6 | RDC_DOMAIN(0)), 69 (RDC_PER_UART7 | RDC_DOMAIN(0)), 70 (RDC_PER_SAI1 | RDC_DOMAIN(0)), 71 (RDC_PER_SAI2 | RDC_DOMAIN(0)), 72 (RDC_PER_SAI3 | RDC_DOMAIN(0)), 73 (RDC_PER_WDOG1 | RDC_DOMAIN(0)), 74 (RDC_PER_WDOG2 | RDC_DOMAIN(0)), 75 (RDC_PER_WDOG3 | RDC_DOMAIN(0)), 76 (RDC_PER_WDOG4 | RDC_DOMAIN(0)), 77 (RDC_PER_GPT1 | RDC_DOMAIN(0)), 78 (RDC_PER_GPT2 | RDC_DOMAIN(0)), 79 (RDC_PER_GPT3 | RDC_DOMAIN(0)), 80 (RDC_PER_GPT4 | RDC_DOMAIN(0)), 81 (RDC_PER_PWM1 | RDC_DOMAIN(0)), 82 (RDC_PER_PWM2 | RDC_DOMAIN(0)), 83 (RDC_PER_PWM3 | RDC_DOMAIN(0)), 84 (RDC_PER_PWM4 | RDC_DOMAIN(0)), 85 (RDC_PER_ENET1 | RDC_DOMAIN(0)), 86 (RDC_PER_ENET2 | RDC_DOMAIN(0)), 87 }; 88 89 static void isolate_resource(void) 90 { 91 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources)); 92 } 93 #endif 94 95 #if defined(CONFIG_SECURE_BOOT) 96 struct imx_sec_config_fuse_t const imx_sec_config_fuse = { 97 .bank = 1, 98 .word = 3, 99 }; 100 #endif 101 102 static bool is_mx7d(void) 103 { 104 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 105 struct fuse_bank *bank = &ocotp->bank[1]; 106 struct fuse_bank1_regs *fuse = 107 (struct fuse_bank1_regs *)bank->fuse_regs; 108 int val; 109 110 val = readl(&fuse->tester4); 111 if (val & 1) 112 return false; 113 else 114 return true; 115 } 116 117 u32 get_cpu_rev(void) 118 { 119 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) 120 ANATOP_BASE_ADDR; 121 u32 reg = readl(&ccm_anatop->digprog); 122 u32 type = (reg >> 16) & 0xff; 123 124 if (!is_mx7d()) 125 type = MXC_CPU_MX7S; 126 127 reg &= 0xff; 128 return (type << 12) | reg; 129 } 130 131 #ifdef CONFIG_REVISION_TAG 132 u32 __weak get_board_rev(void) 133 { 134 return get_cpu_rev(); 135 } 136 #endif 137 138 /* enable all periherial can be accessed in nosec mode */ 139 static void init_csu(void) 140 { 141 int i = 0; 142 for (i = 0; i < CSU_NUM_REGS; i++) 143 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4); 144 } 145 146 static void imx_enet_mdio_fixup(void) 147 { 148 struct iomuxc_gpr_base_regs *gpr_regs = 149 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 150 151 /* 152 * The management data input/output (MDIO) requires open-drain, 153 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports 154 * this feature. So to TO1.1, need to enable open drain by setting 155 * bits GPR0[8:7]. 156 */ 157 158 if (soc_rev() >= CHIP_REV_1_1) { 159 setbits_le32(&gpr_regs->gpr[0], 160 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); 161 } 162 } 163 164 int arch_cpu_init(void) 165 { 166 init_aips(); 167 168 init_csu(); 169 /* Disable PDE bit of WMCR register */ 170 imx_wdog_disable_powerdown(); 171 172 imx_enet_mdio_fixup(); 173 174 #ifdef CONFIG_APBH_DMA 175 /* Start APBH DMA */ 176 mxs_dma_init(); 177 #endif 178 179 #if CONFIG_IS_ENABLED(IMX_RDC) 180 isolate_resource(); 181 #endif 182 183 init_snvs(); 184 185 return 0; 186 } 187 188 #ifdef CONFIG_ARCH_MISC_INIT 189 int arch_misc_init(void) 190 { 191 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 192 if (is_mx7d()) 193 env_set("soc", "imx7d"); 194 else 195 env_set("soc", "imx7s"); 196 #endif 197 198 #ifdef CONFIG_FSL_CAAM 199 sec_init(); 200 #endif 201 202 return 0; 203 } 204 #endif 205 206 #ifdef CONFIG_SERIAL_TAG 207 /* 208 * OCOTP_TESTER 209 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 210 * OCOTP_TESTER describes a unique ID based on silicon wafer 211 * and die X/Y position 212 * 213 * OCOTOP_TESTER offset 0x410 214 * 31:0 fuse 0 215 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID 216 * 217 * OCOTP_TESTER1 offset 0x420 218 * 31:24 fuse 1 219 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 220 * 23:16 fuse 1 221 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 222 * 15:11 fuse 1 223 * The wafer number of the wafer on which the device was fabricated/SJC 224 * CHALLENGE/ Unique ID 225 * 10:0 fuse 1 226 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID 227 */ 228 void get_board_serial(struct tag_serialnr *serialnr) 229 { 230 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 231 struct fuse_bank *bank = &ocotp->bank[0]; 232 struct fuse_bank0_regs *fuse = 233 (struct fuse_bank0_regs *)bank->fuse_regs; 234 235 serialnr->low = fuse->tester0; 236 serialnr->high = fuse->tester1; 237 } 238 #endif 239 240 void set_wdog_reset(struct wdog_regs *wdog) 241 { 242 u32 reg = readw(&wdog->wcr); 243 /* 244 * Output WDOG_B signal to reset external pmic or POR_B decided by 245 * the board desgin. Without external reset, the peripherals/DDR/ 246 * PMIC are not reset, that may cause system working abnormal. 247 */ 248 reg = readw(&wdog->wcr); 249 reg |= 1 << 3; 250 /* 251 * WDZST bit is write-once only bit. Align this bit in kernel, 252 * otherwise kernel code will have no chance to set this bit. 253 */ 254 reg |= 1 << 0; 255 writew(reg, &wdog->wcr); 256 } 257 258 /* 259 * cfg_val will be used for 260 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] 261 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] 262 * to SBMR1, which will determine the boot device. 263 */ 264 const struct boot_mode soc_boot_modes[] = { 265 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)}, 266 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)}, 267 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)}, 268 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)}, 269 270 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)}, 271 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)}, 272 /* 4 bit bus width */ 273 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 274 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)}, 275 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)}, 276 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)}, 277 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)}, 278 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)}, 279 {NULL, 0}, 280 }; 281 282 void s_init(void) 283 { 284 #if !defined CONFIG_SPL_BUILD 285 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ 286 asm volatile( 287 "mrc p15, 0, r0, c1, c0, 1\n" 288 "orr r0, r0, #1 << 6\n" 289 "mcr p15, 0, r0, c1, c0, 1\n"); 290 #endif 291 /* clock configuration. */ 292 clock_init(); 293 294 return; 295 } 296 297 void reset_misc(void) 298 { 299 #ifdef CONFIG_VIDEO_MXS 300 lcdif_power_down(); 301 #endif 302 } 303 304