1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/mach-imx/boot_mode.h> 13 #include <asm/mach-imx/dma.h> 14 #include <asm/mach-imx/hab.h> 15 #include <asm/mach-imx/rdc-sema.h> 16 #include <asm/arch/imx-rdc.h> 17 #include <asm/arch/crm_regs.h> 18 #include <dm.h> 19 #include <imx_thermal.h> 20 21 #if defined(CONFIG_IMX_THERMAL) 22 static const struct imx_thermal_plat imx7_thermal_plat = { 23 .regs = (void *)ANATOP_BASE_ADDR, 24 .fuse_bank = 3, 25 .fuse_word = 3, 26 }; 27 28 U_BOOT_DEVICE(imx7_thermal) = { 29 .name = "imx_thermal", 30 .platdata = &imx7_thermal_plat, 31 }; 32 #endif 33 34 #if CONFIG_IS_ENABLED(IMX_RDC) 35 /* 36 * In current design, if any peripheral was assigned to both A7 and M4, 37 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter 38 * low power mode. So M4 sleep will cause some peripherals fail to work 39 * at A7 core side. At default, all resources are in domain 0 - 3. 40 * 41 * There are 26 peripherals impacted by this IC issue: 42 * SIM2(sim2/emvsim2) 43 * SIM1(sim1/emvsim1) 44 * UART1/UART2/UART3/UART4/UART5/UART6/UART7 45 * SAI1/SAI2/SAI3 46 * WDOG1/WDOG2/WDOG3/WDOG4 47 * GPT1/GPT2/GPT3/GPT4 48 * PWM1/PWM2/PWM3/PWM4 49 * ENET1/ENET2 50 * Software Workaround: 51 * Here we setup some resources to domain 0 where M4 codes will move 52 * the M4 out of this domain. Then M4 is not able to access them any longer. 53 * This is a workaround for ic issue. So the peripherals are not shared 54 * by them. This way requires the uboot implemented the RDC driver and 55 * set the 26 IPs above to domain 0 only. M4 code will assign resource 56 * to its own domain, if it want to use the resource. 57 */ 58 static rdc_peri_cfg_t const resources[] = { 59 (RDC_PER_SIM1 | RDC_DOMAIN(0)), 60 (RDC_PER_SIM2 | RDC_DOMAIN(0)), 61 (RDC_PER_UART1 | RDC_DOMAIN(0)), 62 (RDC_PER_UART2 | RDC_DOMAIN(0)), 63 (RDC_PER_UART3 | RDC_DOMAIN(0)), 64 (RDC_PER_UART4 | RDC_DOMAIN(0)), 65 (RDC_PER_UART5 | RDC_DOMAIN(0)), 66 (RDC_PER_UART6 | RDC_DOMAIN(0)), 67 (RDC_PER_UART7 | RDC_DOMAIN(0)), 68 (RDC_PER_SAI1 | RDC_DOMAIN(0)), 69 (RDC_PER_SAI2 | RDC_DOMAIN(0)), 70 (RDC_PER_SAI3 | RDC_DOMAIN(0)), 71 (RDC_PER_WDOG1 | RDC_DOMAIN(0)), 72 (RDC_PER_WDOG2 | RDC_DOMAIN(0)), 73 (RDC_PER_WDOG3 | RDC_DOMAIN(0)), 74 (RDC_PER_WDOG4 | RDC_DOMAIN(0)), 75 (RDC_PER_GPT1 | RDC_DOMAIN(0)), 76 (RDC_PER_GPT2 | RDC_DOMAIN(0)), 77 (RDC_PER_GPT3 | RDC_DOMAIN(0)), 78 (RDC_PER_GPT4 | RDC_DOMAIN(0)), 79 (RDC_PER_PWM1 | RDC_DOMAIN(0)), 80 (RDC_PER_PWM2 | RDC_DOMAIN(0)), 81 (RDC_PER_PWM3 | RDC_DOMAIN(0)), 82 (RDC_PER_PWM4 | RDC_DOMAIN(0)), 83 (RDC_PER_ENET1 | RDC_DOMAIN(0)), 84 (RDC_PER_ENET2 | RDC_DOMAIN(0)), 85 }; 86 87 static void isolate_resource(void) 88 { 89 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources)); 90 } 91 #endif 92 93 #if defined(CONFIG_SECURE_BOOT) 94 struct imx_sec_config_fuse_t const imx_sec_config_fuse = { 95 .bank = 1, 96 .word = 3, 97 }; 98 #endif 99 100 static bool is_mx7d(void) 101 { 102 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 103 struct fuse_bank *bank = &ocotp->bank[1]; 104 struct fuse_bank1_regs *fuse = 105 (struct fuse_bank1_regs *)bank->fuse_regs; 106 int val; 107 108 val = readl(&fuse->tester4); 109 if (val & 1) 110 return false; 111 else 112 return true; 113 } 114 115 u32 get_cpu_rev(void) 116 { 117 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) 118 ANATOP_BASE_ADDR; 119 u32 reg = readl(&ccm_anatop->digprog); 120 u32 type = (reg >> 16) & 0xff; 121 122 if (!is_mx7d()) 123 type = MXC_CPU_MX7S; 124 125 reg &= 0xff; 126 return (type << 12) | reg; 127 } 128 129 #ifdef CONFIG_REVISION_TAG 130 u32 __weak get_board_rev(void) 131 { 132 return get_cpu_rev(); 133 } 134 #endif 135 136 /* enable all periherial can be accessed in nosec mode */ 137 static void init_csu(void) 138 { 139 int i = 0; 140 for (i = 0; i < CSU_NUM_REGS; i++) 141 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4); 142 } 143 144 static void imx_enet_mdio_fixup(void) 145 { 146 struct iomuxc_gpr_base_regs *gpr_regs = 147 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 148 149 /* 150 * The management data input/output (MDIO) requires open-drain, 151 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports 152 * this feature. So to TO1.1, need to enable open drain by setting 153 * bits GPR0[8:7]. 154 */ 155 156 if (soc_rev() >= CHIP_REV_1_1) { 157 setbits_le32(&gpr_regs->gpr[0], 158 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); 159 } 160 } 161 162 int arch_cpu_init(void) 163 { 164 init_aips(); 165 166 init_csu(); 167 /* Disable PDE bit of WMCR register */ 168 imx_wdog_disable_powerdown(); 169 170 imx_enet_mdio_fixup(); 171 172 #ifdef CONFIG_APBH_DMA 173 /* Start APBH DMA */ 174 mxs_dma_init(); 175 #endif 176 177 #if CONFIG_IS_ENABLED(IMX_RDC) 178 isolate_resource(); 179 #endif 180 181 return 0; 182 } 183 184 #ifdef CONFIG_ARCH_MISC_INIT 185 int arch_misc_init(void) 186 { 187 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 188 if (is_mx7d()) 189 env_set("soc", "imx7d"); 190 else 191 env_set("soc", "imx7s"); 192 #endif 193 194 return 0; 195 } 196 #endif 197 198 #ifdef CONFIG_SERIAL_TAG 199 void get_board_serial(struct tag_serialnr *serialnr) 200 { 201 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 202 struct fuse_bank *bank = &ocotp->bank[0]; 203 struct fuse_bank0_regs *fuse = 204 (struct fuse_bank0_regs *)bank->fuse_regs; 205 206 serialnr->low = fuse->tester0; 207 serialnr->high = fuse->tester1; 208 } 209 #endif 210 211 #if defined(CONFIG_FEC_MXC) 212 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 213 { 214 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 215 struct fuse_bank *bank = &ocotp->bank[9]; 216 struct fuse_bank9_regs *fuse = 217 (struct fuse_bank9_regs *)bank->fuse_regs; 218 219 if (0 == dev_id) { 220 u32 value = readl(&fuse->mac_addr1); 221 mac[0] = (value >> 8); 222 mac[1] = value; 223 224 value = readl(&fuse->mac_addr0); 225 mac[2] = value >> 24; 226 mac[3] = value >> 16; 227 mac[4] = value >> 8; 228 mac[5] = value; 229 } else { 230 u32 value = readl(&fuse->mac_addr2); 231 mac[0] = value >> 24; 232 mac[1] = value >> 16; 233 mac[2] = value >> 8; 234 mac[3] = value; 235 236 value = readl(&fuse->mac_addr1); 237 mac[4] = value >> 24; 238 mac[5] = value >> 16; 239 } 240 } 241 #endif 242 243 #ifdef CONFIG_IMX_BOOTAUX 244 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) 245 { 246 u32 stack, pc; 247 struct src *src_reg = (struct src *)SRC_BASE_ADDR; 248 249 if (!boot_private_data) 250 return 1; 251 252 stack = *(u32 *)boot_private_data; 253 pc = *(u32 *)(boot_private_data + 4); 254 255 /* Set the stack and pc to M4 bootROM */ 256 writel(stack, M4_BOOTROM_BASE_ADDR); 257 writel(pc, M4_BOOTROM_BASE_ADDR + 4); 258 259 /* Enable M4 */ 260 clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK, 261 SRC_M4RCR_ENABLE_M4_MASK); 262 263 return 0; 264 } 265 266 int arch_auxiliary_core_check_up(u32 core_id) 267 { 268 uint32_t val; 269 struct src *src_reg = (struct src *)SRC_BASE_ADDR; 270 271 val = readl(&src_reg->m4rcr); 272 if (val & 0x00000001) 273 return 0; /* assert in reset */ 274 275 return 1; 276 } 277 #endif 278 279 void set_wdog_reset(struct wdog_regs *wdog) 280 { 281 u32 reg = readw(&wdog->wcr); 282 /* 283 * Output WDOG_B signal to reset external pmic or POR_B decided by 284 * the board desgin. Without external reset, the peripherals/DDR/ 285 * PMIC are not reset, that may cause system working abnormal. 286 */ 287 reg = readw(&wdog->wcr); 288 reg |= 1 << 3; 289 /* 290 * WDZST bit is write-once only bit. Align this bit in kernel, 291 * otherwise kernel code will have no chance to set this bit. 292 */ 293 reg |= 1 << 0; 294 writew(reg, &wdog->wcr); 295 } 296 297 /* 298 * cfg_val will be used for 299 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] 300 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] 301 * to SBMR1, which will determine the boot device. 302 */ 303 const struct boot_mode soc_boot_modes[] = { 304 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)}, 305 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)}, 306 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)}, 307 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)}, 308 309 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)}, 310 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)}, 311 /* 4 bit bus width */ 312 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 313 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)}, 314 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)}, 315 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)}, 316 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)}, 317 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)}, 318 {NULL, 0}, 319 }; 320 321 enum boot_device get_boot_device(void) 322 { 323 struct bootrom_sw_info **p = 324 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; 325 326 enum boot_device boot_dev = SD1_BOOT; 327 u8 boot_type = (*p)->boot_dev_type; 328 u8 boot_instance = (*p)->boot_dev_instance; 329 330 switch (boot_type) { 331 case BOOT_TYPE_SD: 332 boot_dev = boot_instance + SD1_BOOT; 333 break; 334 case BOOT_TYPE_MMC: 335 boot_dev = boot_instance + MMC1_BOOT; 336 break; 337 case BOOT_TYPE_NAND: 338 boot_dev = NAND_BOOT; 339 break; 340 case BOOT_TYPE_QSPI: 341 boot_dev = QSPI_BOOT; 342 break; 343 case BOOT_TYPE_WEIM: 344 boot_dev = WEIM_NOR_BOOT; 345 break; 346 case BOOT_TYPE_SPINOR: 347 boot_dev = SPI_NOR_BOOT; 348 break; 349 default: 350 break; 351 } 352 353 return boot_dev; 354 } 355 356 #ifdef CONFIG_ENV_IS_IN_MMC 357 __weak int board_mmc_get_env_dev(int devno) 358 { 359 return CONFIG_SYS_MMC_ENV_DEV; 360 } 361 362 int mmc_get_env_dev(void) 363 { 364 struct bootrom_sw_info **p = 365 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; 366 int devno = (*p)->boot_dev_instance; 367 u8 boot_type = (*p)->boot_dev_type; 368 369 /* If not boot from sd/mmc, use default value */ 370 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) 371 return CONFIG_SYS_MMC_ENV_DEV; 372 373 return board_mmc_get_env_dev(devno); 374 } 375 #endif 376 377 void s_init(void) 378 { 379 #if !defined CONFIG_SPL_BUILD 380 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ 381 asm volatile( 382 "mrc p15, 0, r0, c1, c0, 1\n" 383 "orr r0, r0, #1 << 6\n" 384 "mcr p15, 0, r0, c1, c0, 1\n"); 385 #endif 386 /* clock configuration. */ 387 clock_init(); 388 389 return; 390 } 391 392 void reset_misc(void) 393 { 394 #ifdef CONFIG_VIDEO_MXS 395 lcdif_power_down(); 396 #endif 397 } 398 399