1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2017 NXP 5 */ 6 7 #include <asm/io.h> 8 #include <asm/psci.h> 9 #include <asm/secure.h> 10 #include <asm/arch/imx-regs.h> 11 #include <linux/bitops.h> 12 #include <common.h> 13 #include <fsl_wdog.h> 14 15 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc 16 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 17 #define GPC_PGC_C0 0x800 18 #define GPC_PGC_C1 0x840 19 20 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7 0x1 21 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 22 23 /* below is for i.MX7D */ 24 #define SRC_GPR1_MX7D 0x074 25 #define SRC_A7RCR0 0x004 26 #define SRC_A7RCR1 0x008 27 28 #define BP_SRC_A7RCR0_A7_CORE_RESET0 0 29 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 30 31 #define SNVS_LPCR 0x38 32 #define BP_SNVS_LPCR_DP_EN 0x20 33 #define BP_SNVS_LPCR_TOP 0x40 34 35 #define CCM_CCGR_SNVS 0x4250 36 37 #define CCM_ROOT_WDOG 0xbb80 38 #define CCM_CCGR_WDOG1 0x49c0 39 40 #define MPIDR_AFF0 GENMASK(7, 0) 41 42 #define IMX7D_PSCI_NR_CPUS 2 43 #if IMX7D_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS 44 #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" 45 #endif 46 47 u8 psci_state[IMX7D_PSCI_NR_CPUS] __secure_data = { 48 PSCI_AFFINITY_LEVEL_ON, 49 PSCI_AFFINITY_LEVEL_OFF}; 50 51 static inline void psci_set_state(int cpu, u8 state) 52 { 53 psci_state[cpu] = state; 54 dsb(); 55 isb(); 56 } 57 58 static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) 59 { 60 writel(enable, GPC_IPS_BASE_ADDR + offset); 61 } 62 63 __secure void imx_gpcv2_set_core_power(int cpu, bool pdn) 64 { 65 u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ; 66 u32 pgc = cpu ? GPC_PGC_C1 : GPC_PGC_C0; 67 u32 pdn_pup_req = cpu ? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 : 68 BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7; 69 u32 val; 70 71 imx_gpcv2_set_m_core_pgc(true, pgc); 72 73 val = readl(GPC_IPS_BASE_ADDR + reg); 74 val |= pdn_pup_req; 75 writel(val, GPC_IPS_BASE_ADDR + reg); 76 77 while ((readl(GPC_IPS_BASE_ADDR + reg) & pdn_pup_req) != 0) 78 ; 79 80 imx_gpcv2_set_m_core_pgc(false, pgc); 81 } 82 83 __secure void imx_enable_cpu_ca7(int cpu, bool enable) 84 { 85 u32 mask, val; 86 87 mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1); 88 val = readl(SRC_BASE_ADDR + SRC_A7RCR1); 89 val = enable ? val | mask : val & ~mask; 90 writel(val, SRC_BASE_ADDR + SRC_A7RCR1); 91 } 92 93 __secure void psci_arch_cpu_entry(void) 94 { 95 u32 cpu = psci_get_cpu_id(); 96 97 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); 98 } 99 100 __secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep, 101 u32 context_id) 102 { 103 u32 cpu = mpidr & MPIDR_AFF0; 104 105 if (mpidr & ~MPIDR_AFF0) 106 return ARM_PSCI_RET_INVAL; 107 108 if (cpu >= IMX7D_PSCI_NR_CPUS) 109 return ARM_PSCI_RET_INVAL; 110 111 if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) 112 return ARM_PSCI_RET_ALREADY_ON; 113 114 if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING) 115 return ARM_PSCI_RET_ON_PENDING; 116 117 psci_save(cpu, ep, context_id); 118 119 writel((u32)psci_cpu_entry, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D); 120 121 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING); 122 123 imx_gpcv2_set_core_power(cpu, true); 124 imx_enable_cpu_ca7(cpu, true); 125 126 return ARM_PSCI_RET_SUCCESS; 127 } 128 129 __secure s32 psci_cpu_off(void) 130 { 131 int cpu; 132 133 cpu = psci_get_cpu_id(); 134 135 psci_cpu_off_common(); 136 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); 137 138 imx_enable_cpu_ca7(cpu, false); 139 imx_gpcv2_set_core_power(cpu, false); 140 writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4); 141 142 while (1) 143 wfi(); 144 } 145 146 __secure void psci_system_reset(void) 147 { 148 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 149 150 /* make sure WDOG1 clock is enabled */ 151 writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG); 152 writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1); 153 writew(WCR_WDE, &wdog->wcr); 154 155 while (1) 156 wfi(); 157 } 158 159 __secure void psci_system_off(void) 160 { 161 u32 val; 162 163 /* make sure SNVS clock is enabled */ 164 writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS); 165 166 val = readl(SNVS_BASE_ADDR + SNVS_LPCR); 167 val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP; 168 writel(val, SNVS_BASE_ADDR + SNVS_LPCR); 169 170 while (1) 171 wfi(); 172 } 173 174 __secure u32 psci_version(void) 175 { 176 return ARM_PSCI_VER_1_0; 177 } 178 179 __secure s32 psci_cpu_suspend(u32 __always_unused function_id, u32 power_state, 180 u32 entry_point_address, 181 u32 context_id) 182 { 183 return ARM_PSCI_RET_INVAL; 184 } 185 186 __secure s32 psci_affinity_info(u32 __always_unused function_id, 187 u32 target_affinity, 188 u32 lowest_affinity_level) 189 { 190 u32 cpu = target_affinity & MPIDR_AFF0; 191 192 if (lowest_affinity_level > 0) 193 return ARM_PSCI_RET_INVAL; 194 195 if (target_affinity & ~MPIDR_AFF0) 196 return ARM_PSCI_RET_INVAL; 197 198 if (cpu >= IMX7D_PSCI_NR_CPUS) 199 return ARM_PSCI_RET_INVAL; 200 201 return psci_state[cpu]; 202 } 203 204 __secure s32 psci_migrate_info_type(u32 function_id) 205 { 206 /* Trusted OS is either not present or does not require migration */ 207 return 2; 208 } 209 210 __secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid) 211 { 212 switch (psci_fid) { 213 case ARM_PSCI_0_2_FN_PSCI_VERSION: 214 case ARM_PSCI_0_2_FN_CPU_OFF: 215 case ARM_PSCI_0_2_FN_CPU_ON: 216 case ARM_PSCI_0_2_FN_AFFINITY_INFO: 217 case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 218 case ARM_PSCI_0_2_FN_SYSTEM_OFF: 219 case ARM_PSCI_0_2_FN_SYSTEM_RESET: 220 case ARM_PSCI_1_0_FN_PSCI_FEATURES: 221 return 0x0; 222 } 223 return ARM_PSCI_RET_NI; 224 } 225