1 /* 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 3 * Copyright 2017 NXP 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <asm/io.h> 9 #include <asm/psci.h> 10 #include <asm/secure.h> 11 #include <asm/arch/imx-regs.h> 12 #include <common.h> 13 #include <fsl_wdog.h> 14 15 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc 16 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 17 #define GPC_PGC_C1 0x840 18 19 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 20 21 /* below is for i.MX7D */ 22 #define SRC_GPR1_MX7D 0x074 23 #define SRC_A7RCR0 0x004 24 #define SRC_A7RCR1 0x008 25 26 #define BP_SRC_A7RCR0_A7_CORE_RESET0 0 27 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 28 29 #define SNVS_LPCR 0x38 30 #define BP_SNVS_LPCR_DP_EN 0x20 31 #define BP_SNVS_LPCR_TOP 0x40 32 33 #define CCM_CCGR_SNVS 0x4250 34 35 #define CCM_ROOT_WDOG 0xbb80 36 #define CCM_CCGR_WDOG1 0x49c0 37 38 static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) 39 { 40 writel(enable, GPC_IPS_BASE_ADDR + offset); 41 } 42 43 __secure void imx_gpcv2_set_core1_power(bool pdn) 44 { 45 u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ; 46 u32 val; 47 48 imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); 49 50 val = readl(GPC_IPS_BASE_ADDR + reg); 51 val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; 52 writel(val, GPC_IPS_BASE_ADDR + reg); 53 54 while ((readl(GPC_IPS_BASE_ADDR + reg) & 55 BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0) 56 ; 57 58 imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); 59 } 60 61 __secure void imx_enable_cpu_ca7(int cpu, bool enable) 62 { 63 u32 mask, val; 64 65 mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1); 66 val = readl(SRC_BASE_ADDR + SRC_A7RCR1); 67 val = enable ? val | mask : val & ~mask; 68 writel(val, SRC_BASE_ADDR + SRC_A7RCR1); 69 } 70 71 __secure int imx_cpu_on(int fn, int cpu, int pc) 72 { 73 writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D); 74 imx_gpcv2_set_core1_power(true); 75 imx_enable_cpu_ca7(cpu, true); 76 return 0; 77 } 78 79 __secure int imx_cpu_off(int cpu) 80 { 81 imx_enable_cpu_ca7(cpu, false); 82 imx_gpcv2_set_core1_power(false); 83 writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4); 84 return 0; 85 } 86 87 __secure void imx_system_reset(void) 88 { 89 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 90 91 /* make sure WDOG1 clock is enabled */ 92 writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG); 93 writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1); 94 writew(WCR_WDE, &wdog->wcr); 95 } 96 97 __secure void imx_system_off(void) 98 { 99 u32 val; 100 101 /* make sure SNVS clock is enabled */ 102 writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS); 103 104 val = readl(SNVS_BASE_ADDR + SNVS_LPCR); 105 val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP; 106 writel(val, SNVS_BASE_ADDR + SNVS_LPCR); 107 } 108