1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * Author: 5 * Peng Fan <Peng.Fan@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <div64.h> 12 #include <asm/io.h> 13 #include <linux/errno.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/crm_regs.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/sys_proto.h> 18 19 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) 20 ANATOP_BASE_ADDR; 21 struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 22 23 #ifdef CONFIG_FSL_ESDHC 24 DECLARE_GLOBAL_DATA_PTR; 25 #endif 26 27 int get_clocks(void) 28 { 29 #ifdef CONFIG_FSL_ESDHC 30 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR 31 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 32 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR 33 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 34 #else 35 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 36 #endif 37 #endif 38 return 0; 39 } 40 41 u32 get_ahb_clk(void) 42 { 43 return get_root_clk(AHB_CLK_ROOT); 44 } 45 46 static u32 get_ipg_clk(void) 47 { 48 /* 49 * The AHB and IPG are fixed at 2:1 ratio, and synchronized to 50 * each other. 51 */ 52 return get_ahb_clk() / 2; 53 } 54 55 u32 imx_get_uartclk(void) 56 { 57 return get_root_clk(UART1_CLK_ROOT); 58 } 59 60 u32 imx_get_fecclk(void) 61 { 62 return get_root_clk(ENET_AXI_CLK_ROOT); 63 } 64 65 #ifdef CONFIG_MXC_OCOTP 66 void enable_ocotp_clk(unsigned char enable) 67 { 68 clock_enable(CCGR_OCOTP, enable); 69 } 70 71 void enable_thermal_clk(void) 72 { 73 enable_ocotp_clk(1); 74 } 75 #endif 76 77 void enable_usboh3_clk(unsigned char enable) 78 { 79 u32 target; 80 81 if (enable) { 82 /* disable the clock gate first */ 83 clock_enable(CCGR_USB_HSIC, 0); 84 85 /* 120Mhz */ 86 target = CLK_ROOT_ON | 87 USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | 88 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 89 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 90 clock_set_target_val(USB_HSIC_CLK_ROOT, target); 91 92 /* enable the clock gate */ 93 clock_enable(CCGR_USB_CTRL, 1); 94 clock_enable(CCGR_USB_HSIC, 1); 95 clock_enable(CCGR_USB_PHY1, 1); 96 clock_enable(CCGR_USB_PHY2, 1); 97 } else { 98 clock_enable(CCGR_USB_CTRL, 0); 99 clock_enable(CCGR_USB_HSIC, 0); 100 clock_enable(CCGR_USB_PHY1, 0); 101 clock_enable(CCGR_USB_PHY2, 0); 102 } 103 } 104 105 static u32 decode_pll(enum pll_clocks pll, u32 infreq) 106 { 107 u32 reg, div_sel; 108 u32 num, denom; 109 110 /* 111 * Alought there are four choices for the bypass src, 112 * we choose OSC_24M which is the default set in ROM. 113 */ 114 switch (pll) { 115 case PLL_CORE: 116 reg = readl(&ccm_anatop->pll_arm); 117 118 if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) 119 return 0; 120 121 if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK) 122 return MXC_HCLK; 123 124 div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> 125 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT; 126 127 return (infreq * div_sel) / 2; 128 129 case PLL_SYS: 130 reg = readl(&ccm_anatop->pll_480); 131 132 if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK) 133 return 0; 134 135 if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK) 136 return MXC_HCLK; 137 138 if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >> 139 CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0) 140 return 480000000u; 141 else 142 return 528000000u; 143 144 case PLL_ENET: 145 reg = readl(&ccm_anatop->pll_enet); 146 147 if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) 148 return 0; 149 150 if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK) 151 return MXC_HCLK; 152 153 return 1000000000u; 154 155 case PLL_DDR: 156 reg = readl(&ccm_anatop->pll_ddr); 157 158 if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK) 159 return 0; 160 161 num = ccm_anatop->pll_ddr_num; 162 denom = ccm_anatop->pll_ddr_denom; 163 164 if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK) 165 return MXC_HCLK; 166 167 div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >> 168 CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT; 169 170 return infreq * (div_sel + num / denom); 171 172 case PLL_USB: 173 return 480000000u; 174 175 default: 176 printf("Unsupported pll clocks %d\n", pll); 177 break; 178 } 179 180 return 0; 181 } 182 183 static u32 mxc_get_pll_sys_derive(int derive) 184 { 185 u32 freq, div, frac; 186 u32 reg; 187 188 div = 1; 189 reg = readl(&ccm_anatop->pll_480); 190 freq = decode_pll(PLL_SYS, MXC_HCLK); 191 192 switch (derive) { 193 case PLL_SYS_MAIN_480M_CLK: 194 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK) 195 return 0; 196 else 197 return freq; 198 case PLL_SYS_MAIN_240M_CLK: 199 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK) 200 return 0; 201 else 202 return freq / 2; 203 case PLL_SYS_MAIN_120M_CLK: 204 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK) 205 return 0; 206 else 207 return freq / 4; 208 case PLL_SYS_PFD0_392M_CLK: 209 reg = readl(&ccm_anatop->pfd_480a); 210 if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK) 211 return 0; 212 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> 213 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT; 214 break; 215 case PLL_SYS_PFD0_196M_CLK: 216 if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK) 217 return 0; 218 reg = readl(&ccm_anatop->pfd_480a); 219 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> 220 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT; 221 div = 2; 222 break; 223 case PLL_SYS_PFD1_332M_CLK: 224 reg = readl(&ccm_anatop->pfd_480a); 225 if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK) 226 return 0; 227 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> 228 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT; 229 break; 230 case PLL_SYS_PFD1_166M_CLK: 231 if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK) 232 return 0; 233 reg = readl(&ccm_anatop->pfd_480a); 234 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> 235 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT; 236 div = 2; 237 break; 238 case PLL_SYS_PFD2_270M_CLK: 239 reg = readl(&ccm_anatop->pfd_480a); 240 if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK) 241 return 0; 242 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> 243 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT; 244 break; 245 case PLL_SYS_PFD2_135M_CLK: 246 if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK) 247 return 0; 248 reg = readl(&ccm_anatop->pfd_480a); 249 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> 250 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT; 251 div = 2; 252 break; 253 case PLL_SYS_PFD3_CLK: 254 reg = readl(&ccm_anatop->pfd_480a); 255 if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK) 256 return 0; 257 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >> 258 CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT; 259 break; 260 case PLL_SYS_PFD4_CLK: 261 reg = readl(&ccm_anatop->pfd_480b); 262 if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK) 263 return 0; 264 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >> 265 CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT; 266 break; 267 case PLL_SYS_PFD5_CLK: 268 reg = readl(&ccm_anatop->pfd_480b); 269 if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK) 270 return 0; 271 frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >> 272 CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT; 273 break; 274 case PLL_SYS_PFD6_CLK: 275 reg = readl(&ccm_anatop->pfd_480b); 276 if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK) 277 return 0; 278 frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >> 279 CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT; 280 break; 281 case PLL_SYS_PFD7_CLK: 282 reg = readl(&ccm_anatop->pfd_480b); 283 if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK) 284 return 0; 285 frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >> 286 CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT; 287 break; 288 default: 289 printf("Error derived pll_sys clock %d\n", derive); 290 return 0; 291 } 292 293 return ((freq / frac) * 18) / div; 294 } 295 296 static u32 mxc_get_pll_enet_derive(int derive) 297 { 298 u32 freq, reg; 299 300 freq = decode_pll(PLL_ENET, MXC_HCLK); 301 reg = readl(&ccm_anatop->pll_enet); 302 303 switch (derive) { 304 case PLL_ENET_MAIN_500M_CLK: 305 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK) 306 return freq / 2; 307 break; 308 case PLL_ENET_MAIN_250M_CLK: 309 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK) 310 return freq / 4; 311 break; 312 case PLL_ENET_MAIN_125M_CLK: 313 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK) 314 return freq / 8; 315 break; 316 case PLL_ENET_MAIN_100M_CLK: 317 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK) 318 return freq / 10; 319 break; 320 case PLL_ENET_MAIN_50M_CLK: 321 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK) 322 return freq / 20; 323 break; 324 case PLL_ENET_MAIN_40M_CLK: 325 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK) 326 return freq / 25; 327 break; 328 case PLL_ENET_MAIN_25M_CLK: 329 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK) 330 return freq / 40; 331 break; 332 default: 333 printf("Error derived pll_enet clock %d\n", derive); 334 break; 335 } 336 337 return 0; 338 } 339 340 static u32 mxc_get_pll_ddr_derive(int derive) 341 { 342 u32 freq, reg; 343 344 freq = decode_pll(PLL_DDR, MXC_HCLK); 345 reg = readl(&ccm_anatop->pll_ddr); 346 347 switch (derive) { 348 case PLL_DRAM_MAIN_1066M_CLK: 349 return freq; 350 case PLL_DRAM_MAIN_533M_CLK: 351 if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK) 352 return freq / 2; 353 break; 354 default: 355 printf("Error derived pll_ddr clock %d\n", derive); 356 break; 357 } 358 359 return 0; 360 } 361 362 static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive) 363 { 364 switch (pll) { 365 case PLL_SYS: 366 return mxc_get_pll_sys_derive(derive); 367 case PLL_ENET: 368 return mxc_get_pll_enet_derive(derive); 369 case PLL_DDR: 370 return mxc_get_pll_ddr_derive(derive); 371 default: 372 printf("Error pll.\n"); 373 return 0; 374 } 375 } 376 377 static u32 get_root_src_clk(enum clk_root_src root_src) 378 { 379 switch (root_src) { 380 case OSC_24M_CLK: 381 return 24000000u; 382 case PLL_ARM_MAIN_800M_CLK: 383 return decode_pll(PLL_CORE, MXC_HCLK); 384 385 case PLL_SYS_MAIN_480M_CLK: 386 case PLL_SYS_MAIN_240M_CLK: 387 case PLL_SYS_MAIN_120M_CLK: 388 case PLL_SYS_PFD0_392M_CLK: 389 case PLL_SYS_PFD0_196M_CLK: 390 case PLL_SYS_PFD1_332M_CLK: 391 case PLL_SYS_PFD1_166M_CLK: 392 case PLL_SYS_PFD2_270M_CLK: 393 case PLL_SYS_PFD2_135M_CLK: 394 case PLL_SYS_PFD3_CLK: 395 case PLL_SYS_PFD4_CLK: 396 case PLL_SYS_PFD5_CLK: 397 case PLL_SYS_PFD6_CLK: 398 case PLL_SYS_PFD7_CLK: 399 return mxc_get_pll_derive(PLL_SYS, root_src); 400 401 case PLL_ENET_MAIN_500M_CLK: 402 case PLL_ENET_MAIN_250M_CLK: 403 case PLL_ENET_MAIN_125M_CLK: 404 case PLL_ENET_MAIN_100M_CLK: 405 case PLL_ENET_MAIN_50M_CLK: 406 case PLL_ENET_MAIN_40M_CLK: 407 case PLL_ENET_MAIN_25M_CLK: 408 return mxc_get_pll_derive(PLL_ENET, root_src); 409 410 case PLL_DRAM_MAIN_1066M_CLK: 411 case PLL_DRAM_MAIN_533M_CLK: 412 return mxc_get_pll_derive(PLL_DDR, root_src); 413 414 case PLL_AUDIO_MAIN_CLK: 415 return decode_pll(PLL_AUDIO, MXC_HCLK); 416 case PLL_VIDEO_MAIN_CLK: 417 return decode_pll(PLL_VIDEO, MXC_HCLK); 418 419 case PLL_USB_MAIN_480M_CLK: 420 return decode_pll(PLL_USB, MXC_HCLK); 421 422 case REF_1M_CLK: 423 return 1000000; 424 case OSC_32K_CLK: 425 return MXC_CLK32; 426 427 case EXT_CLK_1: 428 case EXT_CLK_2: 429 case EXT_CLK_3: 430 case EXT_CLK_4: 431 printf("No EXT CLK supported??\n"); 432 break; 433 }; 434 435 return 0; 436 } 437 438 u32 get_root_clk(enum clk_root_index clock_id) 439 { 440 enum clk_root_src root_src; 441 u32 post_podf, pre_podf, auto_podf, root_src_clk; 442 int auto_en; 443 444 if (clock_root_enabled(clock_id) <= 0) 445 return 0; 446 447 if (clock_get_prediv(clock_id, &pre_podf) < 0) 448 return 0; 449 450 if (clock_get_postdiv(clock_id, &post_podf) < 0) 451 return 0; 452 453 if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0) 454 return 0; 455 456 if (auto_en == 0) 457 auto_podf = 0; 458 459 if (clock_get_src(clock_id, &root_src) < 0) 460 return 0; 461 462 root_src_clk = get_root_src_clk(root_src); 463 464 /* 465 * bypass clk is ignored. 466 */ 467 468 return root_src_clk / (post_podf + 1) / (pre_podf + 1) / 469 (auto_podf + 1); 470 } 471 472 static u32 get_ddrc_clk(void) 473 { 474 u32 reg, freq; 475 enum root_post_div post_div; 476 477 reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root); 478 if (reg & CLK_ROOT_MUX_MASK) 479 /* DRAM_ALT_CLK_ROOT */ 480 freq = get_root_clk(DRAM_ALT_CLK_ROOT); 481 else 482 /* PLL_DRAM_MAIN_1066M_CLK */ 483 freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK); 484 485 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK; 486 487 return freq / (post_div + 1) / 2; 488 } 489 490 unsigned int mxc_get_clock(enum mxc_clock clk) 491 { 492 switch (clk) { 493 case MXC_ARM_CLK: 494 return get_root_clk(ARM_A7_CLK_ROOT); 495 case MXC_AXI_CLK: 496 return get_root_clk(MAIN_AXI_CLK_ROOT); 497 case MXC_AHB_CLK: 498 return get_root_clk(AHB_CLK_ROOT); 499 case MXC_IPG_CLK: 500 return get_ipg_clk(); 501 case MXC_I2C_CLK: 502 return get_root_clk(I2C1_CLK_ROOT); 503 case MXC_UART_CLK: 504 return get_root_clk(UART1_CLK_ROOT); 505 case MXC_CSPI_CLK: 506 return get_root_clk(ECSPI1_CLK_ROOT); 507 case MXC_DDR_CLK: 508 return get_ddrc_clk(); 509 case MXC_ESDHC_CLK: 510 return get_root_clk(USDHC1_CLK_ROOT); 511 case MXC_ESDHC2_CLK: 512 return get_root_clk(USDHC2_CLK_ROOT); 513 case MXC_ESDHC3_CLK: 514 return get_root_clk(USDHC3_CLK_ROOT); 515 default: 516 printf("Unsupported mxc_clock %d\n", clk); 517 break; 518 } 519 520 return 0; 521 } 522 523 #ifdef CONFIG_SYS_I2C_MXC 524 /* i2c_num can be 0 - 3 */ 525 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) 526 { 527 u32 target; 528 529 if (i2c_num >= 4) 530 return -EINVAL; 531 532 if (enable) { 533 clock_enable(CCGR_I2C1 + i2c_num, 0); 534 535 /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */ 536 537 target = CLK_ROOT_ON | 538 I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK | 539 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 540 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 541 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target); 542 543 clock_enable(CCGR_I2C1 + i2c_num, 1); 544 } else { 545 clock_enable(CCGR_I2C1 + i2c_num, 0); 546 } 547 548 return 0; 549 } 550 #endif 551 552 static void init_clk_esdhc(void) 553 { 554 u32 target; 555 556 /* disable the clock gate first */ 557 clock_enable(CCGR_USDHC1, 0); 558 clock_enable(CCGR_USDHC2, 0); 559 clock_enable(CCGR_USDHC3, 0); 560 561 /* 196: 392/2 */ 562 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | 563 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 564 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 565 clock_set_target_val(USDHC1_CLK_ROOT, target); 566 567 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | 568 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 569 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 570 clock_set_target_val(USDHC2_CLK_ROOT, target); 571 572 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | 573 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 574 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 575 clock_set_target_val(USDHC3_CLK_ROOT, target); 576 577 /* enable the clock gate */ 578 clock_enable(CCGR_USDHC1, 1); 579 clock_enable(CCGR_USDHC2, 1); 580 clock_enable(CCGR_USDHC3, 1); 581 } 582 583 static void init_clk_uart(void) 584 { 585 u32 target; 586 587 /* disable the clock gate first */ 588 clock_enable(CCGR_UART1, 0); 589 clock_enable(CCGR_UART2, 0); 590 clock_enable(CCGR_UART3, 0); 591 clock_enable(CCGR_UART4, 0); 592 clock_enable(CCGR_UART5, 0); 593 clock_enable(CCGR_UART6, 0); 594 clock_enable(CCGR_UART7, 0); 595 596 /* 24Mhz */ 597 target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK | 598 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 599 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 600 clock_set_target_val(UART1_CLK_ROOT, target); 601 602 target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK | 603 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 604 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 605 clock_set_target_val(UART2_CLK_ROOT, target); 606 607 target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK | 608 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 609 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 610 clock_set_target_val(UART3_CLK_ROOT, target); 611 612 target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK | 613 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 614 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 615 clock_set_target_val(UART4_CLK_ROOT, target); 616 617 target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK | 618 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 619 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 620 clock_set_target_val(UART5_CLK_ROOT, target); 621 622 target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK | 623 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 624 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 625 clock_set_target_val(UART6_CLK_ROOT, target); 626 627 target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK | 628 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 629 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 630 clock_set_target_val(UART7_CLK_ROOT, target); 631 632 /* enable the clock gate */ 633 clock_enable(CCGR_UART1, 1); 634 clock_enable(CCGR_UART2, 1); 635 clock_enable(CCGR_UART3, 1); 636 clock_enable(CCGR_UART4, 1); 637 clock_enable(CCGR_UART5, 1); 638 clock_enable(CCGR_UART6, 1); 639 clock_enable(CCGR_UART7, 1); 640 } 641 642 static void init_clk_weim(void) 643 { 644 u32 target; 645 646 /* disable the clock gate first */ 647 clock_enable(CCGR_WEIM, 0); 648 649 /* 120Mhz */ 650 target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK | 651 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 652 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 653 clock_set_target_val(EIM_CLK_ROOT, target); 654 655 /* enable the clock gate */ 656 clock_enable(CCGR_WEIM, 1); 657 } 658 659 static void init_clk_ecspi(void) 660 { 661 u32 target; 662 663 /* disable the clock gate first */ 664 clock_enable(CCGR_ECSPI1, 0); 665 clock_enable(CCGR_ECSPI2, 0); 666 clock_enable(CCGR_ECSPI3, 0); 667 clock_enable(CCGR_ECSPI4, 0); 668 669 /* 60Mhz: 240/4 */ 670 target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | 671 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 672 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 673 clock_set_target_val(ECSPI1_CLK_ROOT, target); 674 675 target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | 676 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 677 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 678 clock_set_target_val(ECSPI2_CLK_ROOT, target); 679 680 target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | 681 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 682 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 683 clock_set_target_val(ECSPI3_CLK_ROOT, target); 684 685 target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | 686 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 687 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 688 clock_set_target_val(ECSPI4_CLK_ROOT, target); 689 690 /* enable the clock gate */ 691 clock_enable(CCGR_ECSPI1, 1); 692 clock_enable(CCGR_ECSPI2, 1); 693 clock_enable(CCGR_ECSPI3, 1); 694 clock_enable(CCGR_ECSPI4, 1); 695 } 696 697 static void init_clk_wdog(void) 698 { 699 u32 target; 700 701 /* disable the clock gate first */ 702 clock_enable(CCGR_WDOG1, 0); 703 clock_enable(CCGR_WDOG2, 0); 704 clock_enable(CCGR_WDOG3, 0); 705 clock_enable(CCGR_WDOG4, 0); 706 707 /* 24Mhz */ 708 target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK | 709 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 710 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 711 clock_set_target_val(WDOG_CLK_ROOT, target); 712 713 /* enable the clock gate */ 714 clock_enable(CCGR_WDOG1, 1); 715 clock_enable(CCGR_WDOG2, 1); 716 clock_enable(CCGR_WDOG3, 1); 717 clock_enable(CCGR_WDOG4, 1); 718 } 719 720 #ifdef CONFIG_MXC_EPDC 721 static void init_clk_epdc(void) 722 { 723 u32 target; 724 725 /* disable the clock gate first */ 726 clock_enable(CCGR_EPDC, 0); 727 728 /* 24Mhz */ 729 target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | 730 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 731 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12); 732 clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target); 733 734 /* enable the clock gate */ 735 clock_enable(CCGR_EPDC, 1); 736 } 737 #endif 738 739 static int enable_pll_enet(void) 740 { 741 u32 reg; 742 s32 timeout = 100000; 743 744 reg = readl(&ccm_anatop->pll_enet); 745 /* If pll_enet powered up, no need to set it again */ 746 if (reg & ANADIG_PLL_ENET_PWDN_MASK) { 747 reg &= ~ANADIG_PLL_ENET_PWDN_MASK; 748 writel(reg, &ccm_anatop->pll_enet); 749 750 while (timeout--) { 751 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK) 752 break; 753 } 754 755 if (timeout <= 0) { 756 /* If timeout, we set pwdn for pll_enet. */ 757 reg |= ANADIG_PLL_ENET_PWDN_MASK; 758 return -ETIME; 759 } 760 } 761 762 /* Clear bypass */ 763 writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr); 764 765 writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 766 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 767 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 768 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 769 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 770 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 771 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK), 772 &ccm_anatop->pll_enet_set); 773 774 return 0; 775 } 776 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, 777 u32 post_div) 778 { 779 u32 reg = 0; 780 ulong start; 781 782 debug("pll5 div = %d, num = %d, denom = %d\n", 783 pll_div, pll_num, pll_denom); 784 785 /* Power up PLL5 video and disable its output */ 786 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK | 787 CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK | 788 CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK | 789 CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK | 790 CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK | 791 CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK, 792 &ccm_anatop->pll_video_clr); 793 794 /* Set div, num and denom */ 795 switch (post_div) { 796 case 1: 797 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 798 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) | 799 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), 800 &ccm_anatop->pll_video_set); 801 break; 802 case 2: 803 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 804 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | 805 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), 806 &ccm_anatop->pll_video_set); 807 break; 808 case 3: 809 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 810 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | 811 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1), 812 &ccm_anatop->pll_video_set); 813 break; 814 case 4: 815 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 816 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | 817 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3), 818 &ccm_anatop->pll_video_set); 819 break; 820 case 0: 821 default: 822 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 823 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) | 824 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), 825 &ccm_anatop->pll_video_set); 826 break; 827 } 828 829 writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num), 830 &ccm_anatop->pll_video_num); 831 832 writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom), 833 &ccm_anatop->pll_video_denom); 834 835 /* Wait PLL5 lock */ 836 start = get_timer(0); /* Get current timestamp */ 837 838 do { 839 reg = readl(&ccm_anatop->pll_video); 840 if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) { 841 /* Enable PLL out */ 842 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK, 843 &ccm_anatop->pll_video_set); 844 return 0; 845 } 846 } while (get_timer(0) < (start + 10)); /* Wait 10ms */ 847 848 printf("Lock PLL5 timeout\n"); 849 850 return 1; 851 } 852 853 int set_clk_qspi(void) 854 { 855 u32 target; 856 857 /* disable the clock gate first */ 858 clock_enable(CCGR_QSPI, 0); 859 860 /* 49M: 392/2/4 */ 861 target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK | 862 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 863 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 864 clock_set_target_val(QSPI_CLK_ROOT, target); 865 866 /* enable the clock gate */ 867 clock_enable(CCGR_QSPI, 1); 868 869 return 0; 870 } 871 872 int set_clk_nand(void) 873 { 874 u32 target; 875 876 /* disable the clock gate first */ 877 clock_enable(CCGR_RAWNAND, 0); 878 879 enable_pll_enet(); 880 /* 100: 500/5 */ 881 target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK | 882 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 883 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5); 884 clock_set_target_val(NAND_CLK_ROOT, target); 885 886 /* enable the clock gate */ 887 clock_enable(CCGR_RAWNAND, 1); 888 889 return 0; 890 } 891 892 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) 893 { 894 u32 hck = MXC_HCLK/1000; 895 u32 min = hck * 27; 896 u32 max = hck * 54; 897 u32 temp, best = 0; 898 u32 i, j, pred = 1, postd = 1; 899 u32 pll_div, pll_num, pll_denom, post_div = 0; 900 u32 target; 901 902 debug("mxs_set_lcdclk, freq = %d\n", freq); 903 904 clock_enable(CCGR_LCDIF, 0); 905 906 temp = (freq * 8 * 8); 907 if (temp < min) { 908 for (i = 1; i <= 4; i++) { 909 if ((temp * (1 << i)) > min) { 910 post_div = i; 911 freq = (freq * (1 << i)); 912 break; 913 } 914 } 915 916 if (5 == i) { 917 printf("Fail to set rate to %dkhz", freq); 918 return; 919 } 920 } 921 922 for (i = 1; i <= 8; i++) { 923 for (j = 1; j <= 8; j++) { 924 temp = freq * i * j; 925 if (temp > max || temp < min) 926 continue; 927 928 if (best == 0 || temp < best) { 929 best = temp; 930 pred = i; 931 postd = j; 932 } 933 } 934 } 935 936 if (best == 0) { 937 printf("Fail to set rate to %dkhz", freq); 938 return; 939 } 940 941 debug("best %d, pred = %d, postd = %d\n", best, pred, postd); 942 943 pll_div = best / hck; 944 pll_denom = 1000000; 945 pll_num = (best - hck * pll_div) * pll_denom / hck; 946 947 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) 948 return; 949 950 target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK | 951 CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1)); 952 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target); 953 954 clock_enable(CCGR_LCDIF, 1); 955 } 956 957 #ifdef CONFIG_FEC_MXC 958 int set_clk_enet(enum enet_freq type) 959 { 960 u32 target; 961 int ret; 962 u32 enet1_ref, enet2_ref; 963 964 /* disable the clock first */ 965 clock_enable(CCGR_ENET1, 0); 966 clock_enable(CCGR_ENET2, 0); 967 968 switch (type) { 969 case ENET_125MHz: 970 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; 971 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; 972 break; 973 case ENET_50MHz: 974 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; 975 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; 976 break; 977 case ENET_25MHz: 978 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; 979 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; 980 break; 981 default: 982 return -EINVAL; 983 } 984 985 ret = enable_pll_enet(); 986 if (ret != 0) 987 return ret; 988 989 /* set enet axi clock 196M: 392/2 */ 990 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK | 991 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 992 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 993 clock_set_target_val(ENET_AXI_CLK_ROOT, target); 994 995 target = CLK_ROOT_ON | enet1_ref | 996 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 997 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 998 clock_set_target_val(ENET1_REF_CLK_ROOT, target); 999 1000 target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | 1001 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1002 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 1003 clock_set_target_val(ENET1_TIME_CLK_ROOT, target); 1004 1005 target = CLK_ROOT_ON | enet2_ref | 1006 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1007 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 1008 clock_set_target_val(ENET2_REF_CLK_ROOT, target); 1009 1010 target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | 1011 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1012 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 1013 clock_set_target_val(ENET2_TIME_CLK_ROOT, target); 1014 1015 #ifdef CONFIG_FEC_MXC_25M_REF_CLK 1016 target = CLK_ROOT_ON | 1017 ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK | 1018 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1019 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 1020 clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target); 1021 #endif 1022 /* enable clock */ 1023 clock_enable(CCGR_ENET1, 1); 1024 clock_enable(CCGR_ENET2, 1); 1025 1026 return 0; 1027 } 1028 #endif 1029 1030 /* Configure PLL/PFD freq */ 1031 void clock_init(void) 1032 { 1033 /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET 1034 * In u-boot, we have to: 1035 * 1. Configure PFD3- PFD7 for freq we needed in u-boot 1036 * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate 1037 * interface. The clocks for these peripherals are enabled after this intialization. 1038 * 3. Other peripherals with set clock rate interface does not be set in this function. 1039 */ 1040 u32 reg; 1041 1042 /* 1043 * Configure PFD4 to 392M 1044 * 480M * 18 / 0x16 = 392M 1045 */ 1046 reg = readl(&ccm_anatop->pfd_480b); 1047 1048 reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK | 1049 CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK); 1050 reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL; 1051 1052 writel(reg, &ccm_anatop->pfd_480b); 1053 1054 init_clk_esdhc(); 1055 init_clk_uart(); 1056 init_clk_weim(); 1057 init_clk_ecspi(); 1058 init_clk_wdog(); 1059 #ifdef CONFIG_MXC_EPDC 1060 init_clk_epdc(); 1061 #endif 1062 1063 enable_usboh3_clk(1); 1064 1065 clock_enable(CCGR_SNVS, 1); 1066 1067 #ifdef CONFIG_NAND_MXS 1068 clock_enable(CCGR_RAWNAND, 1); 1069 #endif 1070 1071 if (IS_ENABLED(CONFIG_IMX_RDC)) { 1072 clock_enable(CCGR_RDC, 1); 1073 clock_enable(CCGR_SEMA1, 1); 1074 clock_enable(CCGR_SEMA2, 1); 1075 } 1076 } 1077 1078 #ifdef CONFIG_SECURE_BOOT 1079 void hab_caam_clock_enable(unsigned char enable) 1080 { 1081 if (enable) 1082 clock_enable(CCGR_CAAM, 1); 1083 else 1084 clock_enable(CCGR_CAAM, 0); 1085 } 1086 #endif 1087 1088 #ifdef CONFIG_MXC_EPDC 1089 void epdc_clock_enable(void) 1090 { 1091 clock_enable(CCGR_EPDC, 1); 1092 } 1093 void epdc_clock_disable(void) 1094 { 1095 clock_enable(CCGR_EPDC, 0); 1096 } 1097 #endif 1098 1099 /* 1100 * Dump some core clockes. 1101 */ 1102 int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 1103 { 1104 u32 freq; 1105 freq = decode_pll(PLL_CORE, MXC_HCLK); 1106 printf("PLL_CORE %8d MHz\n", freq / 1000000); 1107 freq = decode_pll(PLL_SYS, MXC_HCLK); 1108 printf("PLL_SYS %8d MHz\n", freq / 1000000); 1109 freq = decode_pll(PLL_ENET, MXC_HCLK); 1110 printf("PLL_NET %8d MHz\n", freq / 1000000); 1111 1112 printf("\n"); 1113 1114 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); 1115 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); 1116 #ifdef CONFIG_MXC_SPI 1117 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); 1118 #endif 1119 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); 1120 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); 1121 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); 1122 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); 1123 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); 1124 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); 1125 1126 return 0; 1127 } 1128 1129 U_BOOT_CMD( 1130 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks, 1131 "display clocks", 1132 "" 1133 ); 1134