1 /* 2 * (C) Copyright 2014 3 * Gabriel Huau <contact@huau-gabriel.fr> 4 * 5 * (C) Copyright 2009 Freescale Semiconductor, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <linux/errno.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/arch/imx-regs.h> 15 16 #define MAX_CPUS 4 17 static struct src *src = (struct src *)SRC_BASE_ADDR; 18 19 static uint32_t cpu_reset_mask[MAX_CPUS] = { 20 0, /* We don't really want to modify the cpu0 */ 21 SRC_SCR_CORE_1_RESET_MASK, 22 SRC_SCR_CORE_2_RESET_MASK, 23 SRC_SCR_CORE_3_RESET_MASK 24 }; 25 26 static uint32_t cpu_ctrl_mask[MAX_CPUS] = { 27 0, /* We don't really want to modify the cpu0 */ 28 SRC_SCR_CORE_1_ENABLE_MASK, 29 SRC_SCR_CORE_2_ENABLE_MASK, 30 SRC_SCR_CORE_3_ENABLE_MASK 31 }; 32 33 int cpu_reset(int nr) 34 { 35 /* Software reset of the CPU N */ 36 src->scr |= cpu_reset_mask[nr]; 37 return 0; 38 } 39 40 int cpu_status(int nr) 41 { 42 printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr])); 43 return 0; 44 } 45 46 int cpu_release(int nr, int argc, char *const argv[]) 47 { 48 uint32_t boot_addr; 49 50 boot_addr = simple_strtoul(argv[0], NULL, 16); 51 52 switch (nr) { 53 case 1: 54 src->gpr3 = boot_addr; 55 break; 56 case 2: 57 src->gpr5 = boot_addr; 58 break; 59 case 3: 60 src->gpr7 = boot_addr; 61 break; 62 default: 63 return 1; 64 } 65 66 /* CPU N is ready to start */ 67 src->scr |= cpu_ctrl_mask[nr]; 68 69 return 0; 70 } 71 72 int is_core_valid(unsigned int core) 73 { 74 uint32_t nr_cores = get_nr_cpus(); 75 76 if (core > nr_cores) 77 return 0; 78 79 return 1; 80 } 81 82 int cpu_disable(int nr) 83 { 84 /* Disable the CPU N */ 85 src->scr &= ~cpu_ctrl_mask[nr]; 86 return 0; 87 } 88