1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2018 NXP 4 */ 5 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <dm/device-internal.h> 10 #include <dm/lists.h> 11 #include <dm/uclass.h> 12 #include <errno.h> 13 #include <asm/arch/sci/sci.h> 14 #include <asm/arch-imx/cpu.h> 15 #include <asm/armv8/cpu.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 u32 get_cpu_rev(void) 20 { 21 u32 id = 0, rev = 0; 22 int ret; 23 24 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id); 25 if (ret) 26 return 0; 27 28 rev = (id >> 5) & 0xf; 29 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ 30 31 return (id << 12) | rev; 32 } 33 34 #ifdef CONFIG_DISPLAY_CPUINFO 35 const char *get_imx8_type(u32 imxtype) 36 { 37 switch (imxtype) { 38 case MXC_CPU_IMX8QXP: 39 return "8QXP"; 40 default: 41 return "??"; 42 } 43 } 44 45 const char *get_imx8_rev(u32 rev) 46 { 47 switch (rev) { 48 case CHIP_REV_A: 49 return "A"; 50 case CHIP_REV_B: 51 return "B"; 52 default: 53 return "?"; 54 } 55 } 56 57 const char *get_core_name(void) 58 { 59 if (is_cortex_a35()) 60 return "A35"; 61 else 62 return "?"; 63 } 64 65 int print_cpuinfo(void) 66 { 67 struct udevice *dev; 68 struct clk cpu_clk; 69 int ret; 70 71 ret = uclass_get_device(UCLASS_CPU, 0, &dev); 72 if (ret) 73 return 0; 74 75 ret = clk_get_by_index(dev, 0, &cpu_clk); 76 if (ret) { 77 dev_err(dev, "failed to clk\n"); 78 return 0; 79 } 80 81 u32 cpurev; 82 83 cpurev = get_cpu_rev(); 84 85 printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n", 86 get_imx8_type((cpurev & 0xFF000) >> 12), 87 get_imx8_rev((cpurev & 0xFFF)), 88 get_core_name(), 89 clk_get_rate(&cpu_clk) / 1000000); 90 91 return 0; 92 } 93 #endif 94