1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Toradex, Inc. 4 * 5 * Based on vf610twr: 6 * Copyright 2013 Freescale Semiconductor, Inc. 7 */ 8 9 #include <asm/io.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux-vf610.h> 12 #include <asm/arch/ddrmc-vf610.h> 13 14 void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count) 15 { 16 static const iomux_v3_cfg_t default_pads[] = { 17 VF610_PAD_DDR_A15__DDR_A_15, 18 VF610_PAD_DDR_A14__DDR_A_14, 19 VF610_PAD_DDR_A13__DDR_A_13, 20 VF610_PAD_DDR_A12__DDR_A_12, 21 VF610_PAD_DDR_A11__DDR_A_11, 22 VF610_PAD_DDR_A10__DDR_A_10, 23 VF610_PAD_DDR_A9__DDR_A_9, 24 VF610_PAD_DDR_A8__DDR_A_8, 25 VF610_PAD_DDR_A7__DDR_A_7, 26 VF610_PAD_DDR_A6__DDR_A_6, 27 VF610_PAD_DDR_A5__DDR_A_5, 28 VF610_PAD_DDR_A4__DDR_A_4, 29 VF610_PAD_DDR_A3__DDR_A_3, 30 VF610_PAD_DDR_A2__DDR_A_2, 31 VF610_PAD_DDR_A1__DDR_A_1, 32 VF610_PAD_DDR_A0__DDR_A_0, 33 VF610_PAD_DDR_BA2__DDR_BA_2, 34 VF610_PAD_DDR_BA1__DDR_BA_1, 35 VF610_PAD_DDR_BA0__DDR_BA_0, 36 VF610_PAD_DDR_CAS__DDR_CAS_B, 37 VF610_PAD_DDR_CKE__DDR_CKE_0, 38 VF610_PAD_DDR_CLK__DDR_CLK_0, 39 VF610_PAD_DDR_CS__DDR_CS_B_0, 40 VF610_PAD_DDR_D15__DDR_D_15, 41 VF610_PAD_DDR_D14__DDR_D_14, 42 VF610_PAD_DDR_D13__DDR_D_13, 43 VF610_PAD_DDR_D12__DDR_D_12, 44 VF610_PAD_DDR_D11__DDR_D_11, 45 VF610_PAD_DDR_D10__DDR_D_10, 46 VF610_PAD_DDR_D9__DDR_D_9, 47 VF610_PAD_DDR_D8__DDR_D_8, 48 VF610_PAD_DDR_D7__DDR_D_7, 49 VF610_PAD_DDR_D6__DDR_D_6, 50 VF610_PAD_DDR_D5__DDR_D_5, 51 VF610_PAD_DDR_D4__DDR_D_4, 52 VF610_PAD_DDR_D3__DDR_D_3, 53 VF610_PAD_DDR_D2__DDR_D_2, 54 VF610_PAD_DDR_D1__DDR_D_1, 55 VF610_PAD_DDR_D0__DDR_D_0, 56 VF610_PAD_DDR_DQM1__DDR_DQM_1, 57 VF610_PAD_DDR_DQM0__DDR_DQM_0, 58 VF610_PAD_DDR_DQS1__DDR_DQS_1, 59 VF610_PAD_DDR_DQS0__DDR_DQS_0, 60 VF610_PAD_DDR_RAS__DDR_RAS_B, 61 VF610_PAD_DDR_WE__DDR_WE_B, 62 VF610_PAD_DDR_ODT1__DDR_ODT_0, 63 VF610_PAD_DDR_ODT0__DDR_ODT_1, 64 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, 65 VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2, 66 VF610_PAD_DDR_RESETB, 67 }; 68 69 if ((pads == NULL) || (pads_count == 0)) { 70 pads = default_pads; 71 pads_count = ARRAY_SIZE(default_pads); 72 } 73 74 imx_iomux_v3_setup_multiple_pads(pads, pads_count); 75 } 76 77 static struct ddrmc_phy_setting default_phy_settings[] = { 78 { DDRMC_PHY_DQ_TIMING, 0 }, 79 { DDRMC_PHY_DQ_TIMING, 16 }, 80 { DDRMC_PHY_DQ_TIMING, 32 }, 81 82 { DDRMC_PHY_DQS_TIMING, 1 }, 83 { DDRMC_PHY_DQS_TIMING, 17 }, 84 85 { DDRMC_PHY_CTRL, 2 }, 86 { DDRMC_PHY_CTRL, 18 }, 87 { DDRMC_PHY_CTRL, 34 }, 88 89 { DDRMC_PHY_MASTER_CTRL, 3 }, 90 { DDRMC_PHY_MASTER_CTRL, 19 }, 91 { DDRMC_PHY_MASTER_CTRL, 35 }, 92 93 { DDRMC_PHY_SLAVE_CTRL, 4 }, 94 { DDRMC_PHY_SLAVE_CTRL, 20 }, 95 { DDRMC_PHY_SLAVE_CTRL, 36 }, 96 97 /* LPDDR2 only parameter */ 98 { DDRMC_PHY_OFF, 49 }, 99 100 { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 }, 101 102 /* Processor Pad ODT settings */ 103 { DDRMC_PHY_PROC_PAD_ODT, 52 }, 104 105 /* end marker */ 106 { 0, -1 } 107 }; 108 109 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, 110 struct ddrmc_cr_setting *board_cr_settings, 111 struct ddrmc_phy_setting *board_phy_settings, 112 int col_diff, int row_diff) 113 { 114 struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; 115 struct ddrmc_cr_setting *cr_setting; 116 struct ddrmc_phy_setting *phy_setting; 117 118 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); 119 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); 120 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); 121 122 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); 123 writel(DDRMC_CR12_WRLAT(timings->wrlat) | 124 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); 125 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) | 126 DDRMC_CR13_TCCD(timings->tccd) | 127 DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval), 128 &ddrmr->cr[13]); 129 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | 130 DDRMC_CR14_TWTR(timings->twtr) | 131 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]); 132 writel(DDRMC_CR16_TMRD(timings->tmrd) | 133 DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]); 134 writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) | 135 DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]); 136 writel(DDRMC_CR18_TCKESR(timings->tckesr) | 137 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); 138 139 writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); 140 writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN | 141 DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout), 142 &ddrmr->cr[21]); 143 144 writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]); 145 writel(DDRMC_CR23_BSTLEN(timings->bstlen) | 146 DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]); 147 writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]); 148 149 writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); 150 writel(DDRMC_CR26_TREF(timings->tref) | 151 DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]); 152 writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]); 153 writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]); 154 155 writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]); 156 writel(DDRMC_CR31_TXSNR(timings->txsnr) | 157 DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]); 158 writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); 159 writel(DDRMC_CR34_CKSRX(timings->cksrx) | 160 DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]); 161 162 writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]); 163 writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | 164 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); 165 166 writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]); 167 writel(DDRMC_CR48_MR1_DA_0(70) | 168 DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]); 169 170 writel(DDRMC_CR66_ZQCL(timings->zqcl) | 171 DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]); 172 writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]); 173 writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); 174 175 writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]); 176 writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]); 177 178 writel(DDRMC_CR73_APREBIT(timings->aprebit) | 179 DDRMC_CR73_COL_DIFF(col_diff) | 180 DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]); 181 writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | 182 DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) | 183 DDRMC_CR74_AGE_CNT(timings->age_cnt), 184 &ddrmr->cr[74]); 185 writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | 186 DDRMC_CR75_PLEN, &ddrmr->cr[75]); 187 writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | 188 DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); 189 writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | 190 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); 191 writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) | 192 DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); 193 194 writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); 195 196 writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) | 197 DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0), 198 &ddrmr->cr[87]); 199 writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); 200 writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); 201 202 writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); 203 writel(DDRMC_CR96_WLMRD(timings->wlmrd) | 204 DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]); 205 206 /* execute custom CR setting sequence (may be NULL) */ 207 cr_setting = board_cr_settings; 208 if (cr_setting != NULL) 209 while (cr_setting->cr_rnum >= 0) { 210 writel(cr_setting->setting, 211 &ddrmr->cr[cr_setting->cr_rnum]); 212 cr_setting++; 213 } 214 215 /* perform default PHY settings (may be overridden by custom settings */ 216 phy_setting = default_phy_settings; 217 while (phy_setting->phy_rnum >= 0) { 218 writel(phy_setting->setting, 219 &ddrmr->phy[phy_setting->phy_rnum]); 220 phy_setting++; 221 } 222 223 /* execute custom PHY setting sequence (may be NULL) */ 224 phy_setting = board_phy_settings; 225 if (phy_setting != NULL) 226 while (phy_setting->phy_rnum >= 0) { 227 writel(phy_setting->setting, 228 &ddrmr->phy[phy_setting->phy_rnum]); 229 phy_setting++; 230 } 231 232 /* all inits done, start the DDR controller */ 233 writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); 234 235 while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE)) 236 udelay(10); 237 writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]); 238 } 239