1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * (C) Copyright 2009 Freescale Semiconductor, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <bootm.h> 11 #include <common.h> 12 #include <netdev.h> 13 #include <linux/errno.h> 14 #include <asm/io.h> 15 #include <asm/arch/imx-regs.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/arch/crm_regs.h> 19 #include <asm/mach-imx/boot_mode.h> 20 #include <imx_thermal.h> 21 #include <ipu_pixfmt.h> 22 #include <thermal.h> 23 #include <sata.h> 24 25 #ifdef CONFIG_FSL_ESDHC 26 #include <fsl_esdhc.h> 27 #endif 28 29 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) 30 static u32 reset_cause = -1; 31 32 static char *get_reset_cause(void) 33 { 34 u32 cause; 35 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 36 37 cause = readl(&src_regs->srsr); 38 writel(cause, &src_regs->srsr); 39 reset_cause = cause; 40 41 switch (cause) { 42 case 0x00001: 43 case 0x00011: 44 return "POR"; 45 case 0x00004: 46 return "CSU"; 47 case 0x00008: 48 return "IPP USER"; 49 case 0x00010: 50 #ifdef CONFIG_MX7 51 return "WDOG1"; 52 #else 53 return "WDOG"; 54 #endif 55 case 0x00020: 56 return "JTAG HIGH-Z"; 57 case 0x00040: 58 return "JTAG SW"; 59 case 0x00080: 60 return "WDOG3"; 61 #ifdef CONFIG_MX7 62 case 0x00100: 63 return "WDOG4"; 64 case 0x00200: 65 return "TEMPSENSE"; 66 #elif defined(CONFIG_MX8M) 67 case 0x00100: 68 return "WDOG2"; 69 case 0x00200: 70 return "TEMPSENSE"; 71 #else 72 case 0x00100: 73 return "TEMPSENSE"; 74 case 0x10000: 75 return "WARM BOOT"; 76 #endif 77 default: 78 return "unknown reset"; 79 } 80 } 81 82 u32 get_imx_reset_cause(void) 83 { 84 return reset_cause; 85 } 86 #endif 87 88 #if defined(CONFIG_MX53) || defined(CONFIG_MX6) 89 #if defined(CONFIG_MX53) 90 #define MEMCTL_BASE ESDCTL_BASE_ADDR 91 #else 92 #define MEMCTL_BASE MMDC_P0_BASE_ADDR 93 #endif 94 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; 95 static const unsigned char bank_lookup[] = {3, 2}; 96 97 /* these MMDC registers are common to the IMX53 and IMX6 */ 98 struct esd_mmdc_regs { 99 uint32_t ctl; 100 uint32_t pdc; 101 uint32_t otc; 102 uint32_t cfg0; 103 uint32_t cfg1; 104 uint32_t cfg2; 105 uint32_t misc; 106 }; 107 108 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) 109 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) 110 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) 111 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) 112 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) 113 114 /* 115 * imx_ddr_size - return size in bytes of DRAM according MMDC config 116 * The MMDC MDCTL register holds the number of bits for row, col, and data 117 * width and the MMDC MDMISC register holds the number of banks. Combine 118 * all these bits to determine the meme size the MMDC has been configured for 119 */ 120 unsigned imx_ddr_size(void) 121 { 122 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; 123 unsigned ctl = readl(&mem->ctl); 124 unsigned misc = readl(&mem->misc); 125 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ 126 127 bits += ESD_MMDC_CTL_GET_ROW(ctl); 128 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; 129 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; 130 bits += ESD_MMDC_CTL_GET_WIDTH(ctl); 131 bits += ESD_MMDC_CTL_GET_CS1(ctl); 132 133 /* The MX6 can do only 3840 MiB of DRAM */ 134 if (bits == 32) 135 return 0xf0000000; 136 137 return 1 << bits; 138 } 139 #endif 140 141 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) 142 143 const char *get_imx_type(u32 imxtype) 144 { 145 switch (imxtype) { 146 case MXC_CPU_MX8MQ: 147 return "8MQ"; /* Quad-core version of the mx8m */ 148 case MXC_CPU_MX7S: 149 return "7S"; /* Single-core version of the mx7 */ 150 case MXC_CPU_MX7D: 151 return "7D"; /* Dual-core version of the mx7 */ 152 case MXC_CPU_MX6QP: 153 return "6QP"; /* Quad-Plus version of the mx6 */ 154 case MXC_CPU_MX6DP: 155 return "6DP"; /* Dual-Plus version of the mx6 */ 156 case MXC_CPU_MX6Q: 157 return "6Q"; /* Quad-core version of the mx6 */ 158 case MXC_CPU_MX6D: 159 return "6D"; /* Dual-core version of the mx6 */ 160 case MXC_CPU_MX6DL: 161 return "6DL"; /* Dual Lite version of the mx6 */ 162 case MXC_CPU_MX6SOLO: 163 return "6SOLO"; /* Solo version of the mx6 */ 164 case MXC_CPU_MX6SL: 165 return "6SL"; /* Solo-Lite version of the mx6 */ 166 case MXC_CPU_MX6SLL: 167 return "6SLL"; /* SLL version of the mx6 */ 168 case MXC_CPU_MX6SX: 169 return "6SX"; /* SoloX version of the mx6 */ 170 case MXC_CPU_MX6UL: 171 return "6UL"; /* Ultra-Lite version of the mx6 */ 172 case MXC_CPU_MX6ULL: 173 return "6ULL"; /* ULL version of the mx6 */ 174 case MXC_CPU_MX51: 175 return "51"; 176 case MXC_CPU_MX53: 177 return "53"; 178 default: 179 return "??"; 180 } 181 } 182 183 int print_cpuinfo(void) 184 { 185 u32 cpurev; 186 __maybe_unused u32 max_freq; 187 188 cpurev = get_cpu_rev(); 189 190 #if defined(CONFIG_IMX_THERMAL) 191 struct udevice *thermal_dev; 192 int cpu_tmp, minc, maxc, ret; 193 194 printf("CPU: Freescale i.MX%s rev%d.%d", 195 get_imx_type((cpurev & 0xFF000) >> 12), 196 (cpurev & 0x000F0) >> 4, 197 (cpurev & 0x0000F) >> 0); 198 max_freq = get_cpu_speed_grade_hz(); 199 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) { 200 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); 201 } else { 202 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000, 203 mxc_get_clock(MXC_ARM_CLK) / 1000000); 204 } 205 #else 206 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", 207 get_imx_type((cpurev & 0xFF000) >> 12), 208 (cpurev & 0x000F0) >> 4, 209 (cpurev & 0x0000F) >> 0, 210 mxc_get_clock(MXC_ARM_CLK) / 1000000); 211 #endif 212 213 #if defined(CONFIG_IMX_THERMAL) 214 puts("CPU: "); 215 switch (get_cpu_temp_grade(&minc, &maxc)) { 216 case TEMP_AUTOMOTIVE: 217 puts("Automotive temperature grade "); 218 break; 219 case TEMP_INDUSTRIAL: 220 puts("Industrial temperature grade "); 221 break; 222 case TEMP_EXTCOMMERCIAL: 223 puts("Extended Commercial temperature grade "); 224 break; 225 default: 226 puts("Commercial temperature grade "); 227 break; 228 } 229 printf("(%dC to %dC)", minc, maxc); 230 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); 231 if (!ret) { 232 ret = thermal_get_temp(thermal_dev, &cpu_tmp); 233 234 if (!ret) 235 printf(" at %dC\n", cpu_tmp); 236 else 237 debug(" - invalid sensor data\n"); 238 } else { 239 debug(" - invalid sensor device\n"); 240 } 241 #endif 242 243 printf("Reset cause: %s\n", get_reset_cause()); 244 return 0; 245 } 246 #endif 247 248 int cpu_eth_init(bd_t *bis) 249 { 250 int rc = -ENODEV; 251 252 #if defined(CONFIG_FEC_MXC) 253 rc = fecmxc_initialize(bis); 254 #endif 255 256 return rc; 257 } 258 259 #ifdef CONFIG_FSL_ESDHC 260 /* 261 * Initializes on-chip MMC controllers. 262 * to override, implement board_mmc_init() 263 */ 264 int cpu_mmc_init(bd_t *bis) 265 { 266 return fsl_esdhc_mmc_init(bis); 267 } 268 #endif 269 270 #if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M)) 271 u32 get_ahb_clk(void) 272 { 273 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 274 u32 reg, ahb_podf; 275 276 reg = __raw_readl(&imx_ccm->cbcdr); 277 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; 278 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; 279 280 return get_periph_clk() / (ahb_podf + 1); 281 } 282 #endif 283 284 void arch_preboot_os(void) 285 { 286 #if defined(CONFIG_PCIE_IMX) 287 imx_pcie_remove(); 288 #endif 289 #if defined(CONFIG_SATA) 290 sata_remove(0); 291 #if defined(CONFIG_MX6) 292 disable_sata_clock(); 293 #endif 294 #endif 295 #if defined(CONFIG_VIDEO_IPUV3) 296 /* disable video before launching O/S */ 297 ipuv3_fb_shutdown(); 298 #endif 299 #if defined(CONFIG_VIDEO_MXS) 300 lcdif_power_down(); 301 #endif 302 } 303 304 #ifndef CONFIG_MX8M 305 void set_chipselect_size(int const cs_size) 306 { 307 unsigned int reg; 308 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 309 reg = readl(&iomuxc_regs->gpr[1]); 310 311 switch (cs_size) { 312 case CS0_128: 313 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ 314 reg |= 0x5; 315 break; 316 case CS0_64M_CS1_64M: 317 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ 318 reg |= 0x1B; 319 break; 320 case CS0_64M_CS1_32M_CS2_32M: 321 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ 322 reg |= 0x4B; 323 break; 324 case CS0_32M_CS1_32M_CS2_32M_CS3_32M: 325 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ 326 reg |= 0x249; 327 break; 328 default: 329 printf("Unknown chip select size: %d\n", cs_size); 330 break; 331 } 332 333 writel(reg, &iomuxc_regs->gpr[1]); 334 } 335 #endif 336 337 #if defined(CONFIG_MX7) || defined(CONFIG_MX8M) 338 /* 339 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) 340 * defines a 2-bit SPEED_GRADING 341 */ 342 #define OCOTP_TESTER3_SPEED_SHIFT 8 343 enum cpu_speed { 344 OCOTP_TESTER3_SPEED_GRADE0, 345 OCOTP_TESTER3_SPEED_GRADE1, 346 OCOTP_TESTER3_SPEED_GRADE2, 347 OCOTP_TESTER3_SPEED_GRADE3, 348 }; 349 350 u32 get_cpu_speed_grade_hz(void) 351 { 352 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 353 struct fuse_bank *bank = &ocotp->bank[1]; 354 struct fuse_bank1_regs *fuse = 355 (struct fuse_bank1_regs *)bank->fuse_regs; 356 uint32_t val; 357 358 val = readl(&fuse->tester3); 359 val >>= OCOTP_TESTER3_SPEED_SHIFT; 360 val &= 0x3; 361 362 switch(val) { 363 case OCOTP_TESTER3_SPEED_GRADE0: 364 return 800000000; 365 case OCOTP_TESTER3_SPEED_GRADE1: 366 return is_mx7() ? 500000000 : 1000000000; 367 case OCOTP_TESTER3_SPEED_GRADE2: 368 return is_mx7() ? 1000000000 : 1300000000; 369 case OCOTP_TESTER3_SPEED_GRADE3: 370 return is_mx7() ? 1200000000 : 1500000000; 371 } 372 373 return 0; 374 } 375 376 /* 377 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440) 378 * defines a 2-bit SPEED_GRADING 379 */ 380 #define OCOTP_TESTER3_TEMP_SHIFT 6 381 382 u32 get_cpu_temp_grade(int *minc, int *maxc) 383 { 384 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 385 struct fuse_bank *bank = &ocotp->bank[1]; 386 struct fuse_bank1_regs *fuse = 387 (struct fuse_bank1_regs *)bank->fuse_regs; 388 uint32_t val; 389 390 val = readl(&fuse->tester3); 391 val >>= OCOTP_TESTER3_TEMP_SHIFT; 392 val &= 0x3; 393 394 if (minc && maxc) { 395 if (val == TEMP_AUTOMOTIVE) { 396 *minc = -40; 397 *maxc = 125; 398 } else if (val == TEMP_INDUSTRIAL) { 399 *minc = -40; 400 *maxc = 105; 401 } else if (val == TEMP_EXTCOMMERCIAL) { 402 *minc = -20; 403 *maxc = 105; 404 } else { 405 *minc = 0; 406 *maxc = 95; 407 } 408 } 409 return val; 410 } 411 #endif 412 413 #if defined(CONFIG_MX7) || defined(CONFIG_MX8M) 414 enum boot_device get_boot_device(void) 415 { 416 struct bootrom_sw_info **p = 417 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR; 418 419 enum boot_device boot_dev = SD1_BOOT; 420 u8 boot_type = (*p)->boot_dev_type; 421 u8 boot_instance = (*p)->boot_dev_instance; 422 423 switch (boot_type) { 424 case BOOT_TYPE_SD: 425 boot_dev = boot_instance + SD1_BOOT; 426 break; 427 case BOOT_TYPE_MMC: 428 boot_dev = boot_instance + MMC1_BOOT; 429 break; 430 case BOOT_TYPE_NAND: 431 boot_dev = NAND_BOOT; 432 break; 433 case BOOT_TYPE_QSPI: 434 boot_dev = QSPI_BOOT; 435 break; 436 case BOOT_TYPE_WEIM: 437 boot_dev = WEIM_NOR_BOOT; 438 break; 439 case BOOT_TYPE_SPINOR: 440 boot_dev = SPI_NOR_BOOT; 441 break; 442 #ifdef CONFIG_MX8M 443 case BOOT_TYPE_USB: 444 boot_dev = USB_BOOT; 445 break; 446 #endif 447 default: 448 break; 449 } 450 451 return boot_dev; 452 } 453 #endif 454 455 #ifdef CONFIG_NXP_BOARD_REVISION 456 int nxp_board_rev(void) 457 { 458 /* 459 * Get Board ID information from OCOTP_GP1[15:8] 460 * RevA: 0x1 461 * RevB: 0x2 462 * RevC: 0x3 463 */ 464 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 465 struct fuse_bank *bank = &ocotp->bank[4]; 466 struct fuse_bank4_regs *fuse = 467 (struct fuse_bank4_regs *)bank->fuse_regs; 468 469 return (readl(&fuse->gp1) >> 8 & 0x0F); 470 } 471 472 char nxp_board_rev_string(void) 473 { 474 const char *rev = "A"; 475 476 return (*rev + nxp_board_rev() - 1); 477 } 478 #endif 479