1 /* Copyright (c) 2012 Samsung Electronics Co. Ltd 2 * 3 * Exynos Phy register definitions 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_XHCI_EXYNOS_H_ 9 #define _ASM_ARCH_XHCI_EXYNOS_H_ 10 11 /* Phy register MACRO definitions */ 12 13 #define LINKSYSTEM_FLADJ_MASK (0x3f << 1) 14 #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) 15 #define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) 16 17 #define PHYUTMI_OTGDISABLE (1 << 6) 18 #define PHYUTMI_FORCESUSPEND (1 << 1) 19 #define PHYUTMI_FORCESLEEP (1 << 0) 20 21 #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) 22 #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) 23 24 #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) 25 #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) 26 27 #define PHYCLKRST_SSC_EN (0x1 << 20) 28 #define PHYCLKRST_REF_SSP_EN (0x1 << 19) 29 #define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) 30 31 #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) 32 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) 33 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) 34 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) 35 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) 36 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) 37 38 #define PHYCLKRST_FSEL_MASK (0x3f << 5) 39 #define PHYCLKRST_FSEL(_x) ((_x) << 5) 40 #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) 41 #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) 42 #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) 43 #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) 44 45 #define PHYCLKRST_RETENABLEN (0x1 << 4) 46 47 #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) 48 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) 49 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) 50 51 #define PHYCLKRST_PORTRESET (0x1 << 1) 52 #define PHYCLKRST_COMMONONN (0x1 << 0) 53 54 #define PHYPARAM0_REF_USE_PAD (0x1 << 31) 55 #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) 56 #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) 57 58 #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) 59 #define PHYPARAM1_PCS_TXDEEMPH (0x1c) 60 61 #define PHYTEST_POWERDOWN_SSP (0x1 << 3) 62 #define PHYTEST_POWERDOWN_HSP (0x1 << 2) 63 64 #define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) 65 66 #define FSEL_CLKSEL_24M (0x5) 67 68 /* XHCI PHY register structure */ 69 struct exynos_usb3_phy { 70 unsigned int reserve1; 71 unsigned int link_system; 72 unsigned int phy_utmi; 73 unsigned int phy_pipe; 74 unsigned int phy_clk_rst; 75 unsigned int phy_reg0; 76 unsigned int phy_reg1; 77 unsigned int phy_param0; 78 unsigned int phy_param1; 79 unsigned int phy_term; 80 unsigned int phy_test; 81 unsigned int phy_adp; 82 unsigned int phy_batchg; 83 unsigned int phy_resume; 84 unsigned int reserve2[3]; 85 unsigned int link_port; 86 }; 87 88 #endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */ 89