1 /* 2 * (C) Copyright 2012 Samsung Electronics 3 * Donghwa Lee <dh09.lee@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __ASM_ARM_ARCH_SYSTEM_H_ 9 #define __ASM_ARM_ARCH_SYSTEM_H_ 10 11 #ifndef __ASSEMBLY__ 12 struct exynos4_sysreg { 13 unsigned char res1[0x210]; 14 unsigned int display_ctrl; 15 unsigned int display_ctrl2; 16 unsigned int camera_control; 17 unsigned int audio_endian; 18 unsigned int jtag_con; 19 }; 20 21 struct exynos5_sysreg { 22 unsigned char res1[0x214]; 23 unsigned int disp1blk_cfg; 24 unsigned int disp2blk_cfg; 25 unsigned int hdcp_e_fuse; 26 unsigned int gsclblk_cfg0; 27 unsigned int gsclblk_cfg1; 28 unsigned int reserved; 29 unsigned int ispblk_cfg; 30 unsigned int usb20phy_cfg; 31 unsigned char res2[0x29c]; 32 unsigned int mipi_dphy; 33 unsigned int dptx_dphy; 34 unsigned int phyclk_sel; 35 }; 36 #endif 37 38 #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) 39 40 /* 41 * Data Synchronization Barrier acts as a special kind of memory barrier. 42 * No instruction in program order after this instruction executes until 43 * this instruction completes. This instruction completes when: 44 * - All explicit memory accesses before this instruction complete. 45 * - All Cache, Branch predictor and TLB maintenance operations before 46 * this instruction complete. 47 */ 48 #define dsb() __asm__ __volatile__ ("dsb\n\t" : : ); 49 50 /* 51 * This instruction causes an event to be signaled to all cores 52 * within a multiprocessor system. If SEV is implemented, 53 * WFE must also be implemented. 54 */ 55 #define sev() __asm__ __volatile__ ("sev\n\t" : : ); 56 /* 57 * If the Event Register is not set, WFE suspends execution until 58 * one of the following events occurs: 59 * - an IRQ interrupt, unless masked by the CPSR I-bit 60 * - an FIQ interrupt, unless masked by the CPSR F-bit 61 * - an Imprecise Data abort, unless masked by the CPSR A-bit 62 * - a Debug Entry request, if Debug is enabled 63 * - an Event signaled by another processor using the SEV instruction. 64 * If the Event Register is set, WFE clears it and returns immediately. 65 * If WFE is implemented, SEV must also be implemented. 66 */ 67 #define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); 68 69 /* Move 0xd3 value to CPSR register to enable SVC mode */ 70 #define svc32_mode_en() __asm__ __volatile__ \ 71 ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ 72 "msr cpsr_c, #0x13|0xC0\n\t" : : ) 73 74 /* Set program counter with the given value */ 75 #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) 76 77 /* Branch to the given location */ 78 #define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x)) 79 80 /* Read Main Id register */ 81 #define mrc_midr(x) __asm__ __volatile__ \ 82 ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : ) 83 84 /* Read Multiprocessor Affinity Register */ 85 #define mrc_mpafr(x) __asm__ __volatile__ \ 86 ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : ) 87 88 /* Read System Control Register */ 89 #define mrc_sctlr(x) __asm__ __volatile__ \ 90 ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : ) 91 92 /* Read Auxiliary Control Register */ 93 #define mrc_auxr(x) __asm__ __volatile__ \ 94 ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : ) 95 96 /* Read L2 Control register */ 97 #define mrc_l2_ctlr(x) __asm__ __volatile__ \ 98 ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : ) 99 100 /* Read L2 Auxilliary Control register */ 101 #define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \ 102 ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : ) 103 104 /* Write System Control Register */ 105 #define mcr_sctlr(x) __asm__ __volatile__ \ 106 ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x)) 107 108 /* Write Auxiliary Control Register */ 109 #define mcr_auxr(x) __asm__ __volatile__ \ 110 ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x)) 111 112 /* Invalidate all instruction caches to PoU */ 113 #define mcr_icache(x) __asm__ __volatile__ \ 114 ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x)) 115 116 /* Invalidate unified TLB */ 117 #define mcr_tlb(x) __asm__ __volatile__ \ 118 ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x)) 119 120 /* Write L2 Control register */ 121 #define mcr_l2_ctlr(x) __asm__ __volatile__ \ 122 ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x)) 123 124 /* Write L2 Auxilliary Control register */ 125 #define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \ 126 ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x)) 127 128 void set_usbhost_mode(unsigned int mode); 129 void set_system_display_ctrl(void); 130 int exynos_lcd_early_init(const void *blob); 131 132 #endif /* _EXYNOS4_SYSTEM_H */ 133