1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Padmavathi Venna <padma.v@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_ 9 #define __ASM_ARCH_EXYNOS_COMMON_SPI_H_ 10 11 #ifndef __ASSEMBLY__ 12 13 /* SPI peripheral register map; padded to 64KB */ 14 struct exynos_spi { 15 unsigned int ch_cfg; /* 0x00 */ 16 unsigned char reserved0[4]; 17 unsigned int mode_cfg; /* 0x08 */ 18 unsigned int cs_reg; /* 0x0c */ 19 unsigned char reserved1[4]; 20 unsigned int spi_sts; /* 0x14 */ 21 unsigned int tx_data; /* 0x18 */ 22 unsigned int rx_data; /* 0x1c */ 23 unsigned int pkt_cnt; /* 0x20 */ 24 unsigned char reserved2[4]; 25 unsigned int swap_cfg; /* 0x28 */ 26 unsigned int fb_clk; /* 0x2c */ 27 unsigned char padding[0xffd0]; 28 }; 29 30 #define EXYNOS_SPI_MAX_FREQ 50000000 31 32 #define SPI_TIMEOUT_MS 10 33 #define SF_READ_DATA_CMD 0x3 34 35 /* SPI_CHCFG */ 36 #define SPI_CH_HS_EN (1 << 6) 37 #define SPI_CH_RST (1 << 5) 38 #define SPI_SLAVE_MODE (1 << 4) 39 #define SPI_CH_CPOL_L (1 << 3) 40 #define SPI_CH_CPHA_B (1 << 2) 41 #define SPI_RX_CH_ON (1 << 1) 42 #define SPI_TX_CH_ON (1 << 0) 43 44 /* SPI_MODECFG */ 45 #define SPI_MODE_CH_WIDTH_WORD (0x2 << 29) 46 #define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17) 47 48 /* SPI_CSREG */ 49 #define SPI_SLAVE_SIG_INACT (1 << 0) 50 51 /* SPI_STS */ 52 #define SPI_ST_TX_DONE (1 << 25) 53 #define SPI_FIFO_LVL_MASK 0x1ff 54 #define SPI_TX_LVL_OFFSET 6 55 #define SPI_RX_LVL_OFFSET 15 56 57 /* Feedback Delay */ 58 #define SPI_CLK_BYPASS (0 << 0) 59 #define SPI_FB_DELAY_90 (1 << 0) 60 #define SPI_FB_DELAY_180 (2 << 0) 61 #define SPI_FB_DELAY_270 (3 << 0) 62 63 /* Packet Count */ 64 #define SPI_PACKET_CNT_EN (1 << 16) 65 66 /* Swap config */ 67 #define SPI_TX_SWAP_EN (1 << 0) 68 #define SPI_TX_BYTE_SWAP (1 << 2) 69 #define SPI_TX_HWORD_SWAP (1 << 3) 70 #define SPI_TX_BYTE_SWAP (1 << 2) 71 #define SPI_RX_SWAP_EN (1 << 4) 72 #define SPI_RX_BYTE_SWAP (1 << 6) 73 #define SPI_RX_HWORD_SWAP (1 << 7) 74 75 #endif /* __ASSEMBLY__ */ 76 #endif 77