1 /* 2 * (C) Copyright 2010 Samsung Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _EXYNOS4_CPU_H 9 #define _EXYNOS4_CPU_H 10 11 #define DEVICE_NOT_AVAILABLE 0 12 13 #define EXYNOS_CPU_NAME "Exynos" 14 #define EXYNOS4_ADDR_BASE 0x10000000 15 16 /* EXYNOS4 Common*/ 17 #define EXYNOS4_I2C_SPACING 0x10000 18 19 #define EXYNOS4_GPIO_PART3_BASE 0x03860000 20 #define EXYNOS4_PRO_ID 0x10000000 21 #define EXYNOS4_SYSREG_BASE 0x10010000 22 #define EXYNOS4_POWER_BASE 0x10020000 23 #define EXYNOS4_SWRESET 0x10020400 24 #define EXYNOS4_CLOCK_BASE 0x10030000 25 #define EXYNOS4_SYSTIMER_BASE 0x10050000 26 #define EXYNOS4_WATCHDOG_BASE 0x10060000 27 #define EXYNOS4_TZPC_BASE 0x10110000 28 #define EXYNOS4_DMC_CTRL_BASE 0x10400000 29 #define EXYNOS4_MIU_BASE 0x10600000 30 #define EXYNOS4_ACE_SFR_BASE 0x10830000 31 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 32 #define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ 33 #define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ 34 #define EXYNOS4_GPIO_PART1_BASE 0x11400000 35 #define EXYNOS4_FIMD_BASE 0x11C00000 36 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 37 #define EXYNOS4_USBOTG_BASE 0x12480000 38 #define EXYNOS4_MMC_BASE 0x12510000 39 #define EXYNOS4_SROMC_BASE 0x12570000 40 #define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000 41 #define EXYNOS4_USBPHY_BASE 0x125B0000 42 #define EXYNOS4_UART_BASE 0x13800000 43 #define EXYNOS4_I2C_BASE 0x13860000 44 #define EXYNOS4_ADC_BASE 0x13910000 45 #define EXYNOS4_SPI_BASE 0x13920000 46 #define EXYNOS4_PWMTIMER_BASE 0x139D0000 47 #define EXYNOS4_MODEM_BASE 0x13A00000 48 #define EXYNOS4_USBPHY_CONTROL 0x10020704 49 #define EXYNOS4_I2S_BASE 0xE2100000 50 51 #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE 52 #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE 53 #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE 54 #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE 55 #define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE 56 #define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE 57 #define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE 58 #define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE 59 60 /* EXYNOS4X12 */ 61 #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 62 #define EXYNOS4X12_PRO_ID 0x10000000 63 #define EXYNOS4X12_SYSREG_BASE 0x10010000 64 #define EXYNOS4X12_POWER_BASE 0x10020000 65 #define EXYNOS4X12_SWRESET 0x10020400 66 #define EXYNOS4X12_USBPHY_CONTROL 0x10020704 67 #define EXYNOS4X12_CLOCK_BASE 0x10030000 68 #define EXYNOS4X12_SYSTIMER_BASE 0x10050000 69 #define EXYNOS4X12_WATCHDOG_BASE 0x10060000 70 #define EXYNOS4X12_TZPC_BASE 0x10110000 71 #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 72 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 73 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000 74 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 75 #define EXYNOS4X12_GPIO_PART2_0 0x11000000 76 #define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ 77 #define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ 78 #define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ 79 #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 80 #define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ 81 #define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ 82 #define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */ 83 #define EXYNOS4X12_FIMD_BASE 0x11C00000 84 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 85 #define EXYNOS4X12_USBOTG_BASE 0x12480000 86 #define EXYNOS4X12_MMC_BASE 0x12510000 87 #define EXYNOS4X12_SROMC_BASE 0x12570000 88 #define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000 89 #define EXYNOS4X12_USBPHY_BASE 0x125B0000 90 #define EXYNOS4X12_UART_BASE 0x13800000 91 #define EXYNOS4X12_I2C_BASE 0x13860000 92 #define EXYNOS4X12_PWMTIMER_BASE 0x139D0000 93 94 #define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE 95 #define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE 96 #define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE 97 #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE 98 #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE 99 #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE 100 #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE 101 #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE 102 #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE 103 #define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE 104 #define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE 105 106 /* EXYNOS5 */ 107 #define EXYNOS5_I2C_SPACING 0x10000 108 109 #define EXYNOS5_AUDIOSS_BASE 0x03810000 110 #define EXYNOS5_GPIO_PART8_BASE 0x03860000 111 #define EXYNOS5_PRO_ID 0x10000000 112 #define EXYNOS5_CLOCK_BASE 0x10010000 113 #define EXYNOS5_POWER_BASE 0x10040000 114 #define EXYNOS5_SWRESET 0x10040400 115 #define EXYNOS5_SYSREG_BASE 0x10050000 116 #define EXYNOS5_TZPC_BASE 0x10100000 117 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 118 #define EXYNOS5_ACE_SFR_BASE 0x10830000 119 #define EXYNOS5_DMC_PHY_BASE 0x10C00000 120 #define EXYNOS5_GPIO_PART5_BASE 0x10D10000 121 #define EXYNOS5_GPIO_PART6_BASE 0x10D10060 122 #define EXYNOS5_GPIO_PART7_BASE 0x10D100C0 123 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 124 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 125 #define EXYNOS5_GPIO_PART2_BASE 0x114002E0 126 #define EXYNOS5_GPIO_PART3_BASE 0x11400C00 127 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 128 #define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000 129 #define EXYNOS5_USB3PHY_BASE 0x12100000 130 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 131 #define EXYNOS5_USBPHY_BASE 0x12130000 132 #define EXYNOS5_USBOTG_BASE 0x12140000 133 #define EXYNOS5_MMC_BASE 0x12200000 134 #define EXYNOS5_SROMC_BASE 0x12250000 135 #define EXYNOS5_UART_BASE 0x12C00000 136 #define EXYNOS5_I2C_BASE 0x12C60000 137 #define EXYNOS5_SPI_BASE 0x12D20000 138 #define EXYNOS5_I2S_BASE 0x12D60000 139 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 140 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 141 #define EXYNOS5_GPIO_PART4_BASE 0x13400000 142 #define EXYNOS5_FIMD_BASE 0x14400000 143 #define EXYNOS5_DP_BASE 0x145B0000 144 145 #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE 146 #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE 147 #define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE 148 149 /* EXYNOS5420 */ 150 #define EXYNOS5420_AUDIOSS_BASE 0x03810000 151 #define EXYNOS5420_GPIO_PART6_BASE 0x03860000 152 #define EXYNOS5420_PRO_ID 0x10000000 153 #define EXYNOS5420_CLOCK_BASE 0x10010000 154 #define EXYNOS5420_POWER_BASE 0x10040000 155 #define EXYNOS5420_SWRESET 0x10040400 156 #define EXYNOS5420_INFORM_BASE 0x10040800 157 #define EXYNOS5420_SPARE_BASE 0x10040900 158 #define EXYNOS5420_CPU_CONFIG_BASE 0x10042000 159 #define EXYNOS5420_CPU_STATUS_BASE 0x10042004 160 #define EXYNOS5420_SYSREG_BASE 0x10050000 161 #define EXYNOS5420_TZPC_BASE 0x100E0000 162 #define EXYNOS5420_WATCHDOG_BASE 0x101D0000 163 #define EXYNOS5420_ACE_SFR_BASE 0x10830000 164 #define EXYNOS5420_DMC_PHY_BASE 0x10C00000 165 #define EXYNOS5420_DMC_CTRL_BASE 0x10C20000 166 #define EXYNOS5420_DMC_TZASC_BASE 0x10D40000 167 #define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000 168 #define EXYNOS5420_MMC_BASE 0x12200000 169 #define EXYNOS5420_SROMC_BASE 0x12250000 170 #define EXYNOS5420_USB3PHY_BASE 0x12500000 171 #define EXYNOS5420_UART_BASE 0x12C00000 172 #define EXYNOS5420_I2C_BASE 0x12C60000 173 #define EXYNOS5420_I2C_8910_BASE 0x12E00000 174 #define EXYNOS5420_SPI_BASE 0x12D20000 175 #define EXYNOS5420_I2S_BASE 0x12D60000 176 #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 177 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000 178 #define EXYNOS5420_GPIO_PART2_BASE 0x13400000 179 #define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 180 #define EXYNOS5420_GPIO_PART4_BASE 0x13410000 181 #define EXYNOS5420_GPIO_PART5_BASE 0x14000000 182 #define EXYNOS5420_GPIO_PART1_BASE 0x14010000 183 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 184 #define EXYNOS5420_DP_BASE 0x145B0000 185 186 #define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE 187 #define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE 188 #define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE 189 #define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE 190 #define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE 191 #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE 192 193 194 #ifndef __ASSEMBLY__ 195 #include <asm/io.h> 196 /* CPU detection macros */ 197 extern unsigned int s5p_cpu_id; 198 extern unsigned int s5p_cpu_rev; 199 200 static inline int s5p_get_cpu_rev(void) 201 { 202 return s5p_cpu_rev; 203 } 204 205 static inline void s5p_set_cpu_id(void) 206 { 207 unsigned int pro_id = readl(EXYNOS4_PRO_ID); 208 unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12; 209 unsigned int cpu_rev = pro_id & 0x000000FF; 210 211 switch (cpu_id) { 212 case 0x200: 213 /* Exynos4210 EVT0 */ 214 s5p_cpu_id = 0x4210; 215 s5p_cpu_rev = 0; 216 break; 217 case 0x210: 218 /* Exynos4210 EVT1 */ 219 s5p_cpu_id = 0x4210; 220 s5p_cpu_rev = cpu_rev; 221 break; 222 case 0x412: 223 /* Exynos4412 */ 224 s5p_cpu_id = 0x4412; 225 s5p_cpu_rev = cpu_rev; 226 break; 227 case 0x520: 228 /* Exynos5250 */ 229 s5p_cpu_id = 0x5250; 230 break; 231 case 0x420: 232 /* Exynos5420 */ 233 s5p_cpu_id = 0x5420; 234 break; 235 case 0x422: 236 /* 237 * Exynos5800 is a variant of Exynos5420 238 * and has product id 0x5422 239 */ 240 s5p_cpu_id = 0x5800; 241 break; 242 } 243 } 244 245 static inline char *s5p_get_cpu_name(void) 246 { 247 return EXYNOS_CPU_NAME; 248 } 249 250 #define IS_SAMSUNG_TYPE(type, id) \ 251 static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \ 252 { \ 253 return (s5p_cpu_id >> 12) == id; \ 254 } 255 256 IS_SAMSUNG_TYPE(exynos4, 0x4) 257 IS_SAMSUNG_TYPE(exynos5, 0x5) 258 259 #define IS_EXYNOS_TYPE(type, id) \ 260 static inline int __attribute__((no_instrument_function)) \ 261 proid_is_##type(void) \ 262 { \ 263 return s5p_cpu_id == id; \ 264 } 265 266 IS_EXYNOS_TYPE(exynos4210, 0x4210) 267 IS_EXYNOS_TYPE(exynos4412, 0x4412) 268 IS_EXYNOS_TYPE(exynos5250, 0x5250) 269 IS_EXYNOS_TYPE(exynos5420, 0x5420) 270 IS_EXYNOS_TYPE(exynos5800, 0x5800) 271 272 #define SAMSUNG_BASE(device, base) \ 273 static inline unsigned int __attribute__((no_instrument_function)) \ 274 samsung_get_base_##device(void) \ 275 { \ 276 if (cpu_is_exynos4()) { \ 277 if (proid_is_exynos4412()) \ 278 return EXYNOS4X12_##base; \ 279 return EXYNOS4_##base; \ 280 } else if (cpu_is_exynos5()) { \ 281 if (proid_is_exynos5420() || proid_is_exynos5800()) \ 282 return EXYNOS5420_##base; \ 283 return EXYNOS5_##base; \ 284 } \ 285 return 0; \ 286 } 287 288 SAMSUNG_BASE(adc, ADC_BASE) 289 SAMSUNG_BASE(clock, CLOCK_BASE) 290 SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) 291 SAMSUNG_BASE(dp, DP_BASE) 292 SAMSUNG_BASE(sysreg, SYSREG_BASE) 293 SAMSUNG_BASE(fimd, FIMD_BASE) 294 SAMSUNG_BASE(i2c, I2C_BASE) 295 SAMSUNG_BASE(i2s, I2S_BASE) 296 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) 297 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) 298 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) 299 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) 300 SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) 301 SAMSUNG_BASE(pro_id, PRO_ID) 302 SAMSUNG_BASE(mmc, MMC_BASE) 303 SAMSUNG_BASE(modem, MODEM_BASE) 304 SAMSUNG_BASE(sromc, SROMC_BASE) 305 SAMSUNG_BASE(swreset, SWRESET) 306 SAMSUNG_BASE(timer, PWMTIMER_BASE) 307 SAMSUNG_BASE(uart, UART_BASE) 308 SAMSUNG_BASE(usb_phy, USBPHY_BASE) 309 SAMSUNG_BASE(usb3_phy, USB3PHY_BASE) 310 SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) 311 SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE) 312 SAMSUNG_BASE(usb_otg, USBOTG_BASE) 313 SAMSUNG_BASE(watchdog, WATCHDOG_BASE) 314 SAMSUNG_BASE(power, POWER_BASE) 315 SAMSUNG_BASE(spi, SPI_BASE) 316 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) 317 SAMSUNG_BASE(tzpc, TZPC_BASE) 318 SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE) 319 SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE) 320 SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE) 321 SAMSUNG_BASE(audio_ass, AUDIOSS_BASE) 322 #endif 323 324 #endif /* _EXYNOS4_CPU_H */ 325