1 /*
2  * Common APIs for EXYNOS based board
3  *
4  * Copyright (C) 2013 Samsung Electronics
5  * Rajeshwari Shinde <rajeshwari.s@samsung.com>
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 #include <asm/arch/system.h>
27 
28 #define DMC_OFFSET	0x10000
29 
30 /*
31  * Memory initialization
32  *
33  * @param reset     Reset PHY during initialization.
34  */
35 void mem_ctrl_init(int reset);
36 
37  /* System Clock initialization */
38 void system_clock_init(void);
39 
40 /*
41  * Init subsystems according to the reset status
42  *
43  * @return 0 for a normal boot, non-zero for a resume
44  */
45 int do_lowlevel_init(void);
46 
47 void sdelay(unsigned long);
48 
49 enum l2_cache_params {
50 	CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
51 	CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
52 	CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
53 	CACHE_DATA_RAM_SETUP = (1 << 5),
54 	CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
55 	CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
56 	CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
57 	CACHE_TAG_RAM_SETUP = (1 << 9),
58 	CACHE_ECC_AND_PARITY = (1 << 21),
59 	CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
60 };
61 
62 
63 #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
64 /*
65  * Configure L2CTLR to get timings that keep us from hanging/crashing.
66  *
67  * Must be inline here since low_power_start() is called without a
68  * stack (!).
69  */
70 static inline void configure_l2_ctlr(void)
71 {
72 	uint32_t val;
73 
74 	mrc_l2_ctlr(val);
75 
76 	val |= CACHE_TAG_RAM_SETUP |
77 		CACHE_DATA_RAM_SETUP |
78 		CACHE_TAG_RAM_LATENCY_2_CYCLES |
79 		CACHE_DATA_RAM_LATENCY_2_CYCLES;
80 
81 	if (proid_is_exynos5420() || proid_is_exynos5422()) {
82 		val |= CACHE_ECC_AND_PARITY |
83 			CACHE_TAG_RAM_LATENCY_3_CYCLES |
84 			CACHE_DATA_RAM_LATENCY_3_CYCLES;
85 	}
86 
87 	mcr_l2_ctlr(val);
88 }
89 
90 /*
91  * Configure L2ACTLR.
92  *
93  * Must be inline here since low_power_start() is called without a
94  * stack (!).
95  */
96 static inline void configure_l2_actlr(void)
97 {
98 	uint32_t val;
99 
100 	if (proid_is_exynos5420() || proid_is_exynos5422()) {
101 		mrc_l2_aux_ctlr(val);
102 		val |= CACHE_ENABLE_FORCE_L2_LOGIC |
103 			CACHE_DISABLE_CLEAN_EVICT;
104 		mcr_l2_aux_ctlr(val);
105 	}
106 }
107 #endif
108