1 /*
2  * Clock setup for SMDK5250 board based on EXYNOS5
3  *
4  * Copyright (C) 2012 Samsung Electronics
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <config.h>
11 #include <asm/io.h>
12 #include <asm/arch/clk.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/spl.h>
15 #include <asm/arch/dwmmc.h>
16 
17 #include "clock_init.h"
18 #include "common_setup.h"
19 #include "exynos5_setup.h"
20 
21 #define FSYS1_MMC0_DIV_MASK	0xff0f
22 #define FSYS1_MMC0_DIV_VAL	0x0701
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 struct arm_clk_ratios arm_clk_ratios[] = {
27 #ifdef CONFIG_EXYNOS5420
28 	{
29 		.arm_freq_mhz = 900,
30 
31 		.apll_mdiv = 0x96,
32 		.apll_pdiv = 0x2,
33 		.apll_sdiv = 0x1,
34 
35 		.arm2_ratio = 0x0,
36 		.apll_ratio = 0x3,
37 		.pclk_dbg_ratio = 0x6,
38 		.atb_ratio = 0x6,
39 		.periph_ratio = 0x7,
40 		.acp_ratio = 0x0,
41 		.cpud_ratio = 0x2,
42 		.arm_ratio = 0x0,
43 	}
44 #else
45 	{
46 		.arm_freq_mhz = 600,
47 
48 		.apll_mdiv = 0xc8,
49 		.apll_pdiv = 0x4,
50 		.apll_sdiv = 0x1,
51 
52 		.arm2_ratio = 0x0,
53 		.apll_ratio = 0x1,
54 		.pclk_dbg_ratio = 0x1,
55 		.atb_ratio = 0x2,
56 		.periph_ratio = 0x7,
57 		.acp_ratio = 0x7,
58 		.cpud_ratio = 0x1,
59 		.arm_ratio = 0x0,
60 	}, {
61 		.arm_freq_mhz = 800,
62 
63 		.apll_mdiv = 0x64,
64 		.apll_pdiv = 0x3,
65 		.apll_sdiv = 0x0,
66 
67 		.arm2_ratio = 0x0,
68 		.apll_ratio = 0x1,
69 		.pclk_dbg_ratio = 0x1,
70 		.atb_ratio = 0x3,
71 		.periph_ratio = 0x7,
72 		.acp_ratio = 0x7,
73 		.cpud_ratio = 0x2,
74 		.arm_ratio = 0x0,
75 	}, {
76 		.arm_freq_mhz = 1000,
77 
78 		.apll_mdiv = 0x7d,
79 		.apll_pdiv = 0x3,
80 		.apll_sdiv = 0x0,
81 
82 		.arm2_ratio = 0x0,
83 		.apll_ratio = 0x1,
84 		.pclk_dbg_ratio = 0x1,
85 		.atb_ratio = 0x4,
86 		.periph_ratio = 0x7,
87 		.acp_ratio = 0x7,
88 		.cpud_ratio = 0x2,
89 		.arm_ratio = 0x0,
90 	}, {
91 		.arm_freq_mhz = 1200,
92 
93 		.apll_mdiv = 0x96,
94 		.apll_pdiv = 0x3,
95 		.apll_sdiv = 0x0,
96 
97 		.arm2_ratio = 0x0,
98 		.apll_ratio = 0x3,
99 		.pclk_dbg_ratio = 0x1,
100 		.atb_ratio = 0x5,
101 		.periph_ratio = 0x7,
102 		.acp_ratio = 0x7,
103 		.cpud_ratio = 0x3,
104 		.arm_ratio = 0x0,
105 	}, {
106 		.arm_freq_mhz = 1400,
107 
108 		.apll_mdiv = 0xaf,
109 		.apll_pdiv = 0x3,
110 		.apll_sdiv = 0x0,
111 
112 		.arm2_ratio = 0x0,
113 		.apll_ratio = 0x3,
114 		.pclk_dbg_ratio = 0x1,
115 		.atb_ratio = 0x6,
116 		.periph_ratio = 0x7,
117 		.acp_ratio = 0x7,
118 		.cpud_ratio = 0x3,
119 		.arm_ratio = 0x0,
120 	}, {
121 		.arm_freq_mhz = 1700,
122 
123 		.apll_mdiv = 0x1a9,
124 		.apll_pdiv = 0x6,
125 		.apll_sdiv = 0x0,
126 
127 		.arm2_ratio = 0x0,
128 		.apll_ratio = 0x3,
129 		.pclk_dbg_ratio = 0x1,
130 		.atb_ratio = 0x6,
131 		.periph_ratio = 0x7,
132 		.acp_ratio = 0x7,
133 		.cpud_ratio = 0x3,
134 		.arm_ratio = 0x0,
135 	}
136 #endif
137 };
138 
139 struct mem_timings mem_timings[] = {
140 #ifdef CONFIG_EXYNOS5420
141 	{
142 		.mem_manuf = MEM_MANUF_SAMSUNG,
143 		.mem_type = DDR_MODE_DDR3,
144 		.frequency_mhz = 800,
145 
146 		/* MPLL @800MHz*/
147 		.mpll_mdiv = 0xc8,
148 		.mpll_pdiv = 0x3,
149 		.mpll_sdiv = 0x1,
150 		/* CPLL @666MHz */
151 		.cpll_mdiv = 0xde,
152 		.cpll_pdiv = 0x4,
153 		.cpll_sdiv = 0x1,
154 		/* EPLL @600MHz */
155 		.epll_mdiv = 0x64,
156 		.epll_pdiv = 0x2,
157 		.epll_sdiv = 0x1,
158 		/* VPLL @430MHz */
159 		.vpll_mdiv = 0xd7,
160 		.vpll_pdiv = 0x3,
161 		.vpll_sdiv = 0x2,
162 		/* BPLL @800MHz */
163 		.bpll_mdiv = 0xc8,
164 		.bpll_pdiv = 0x3,
165 		.bpll_sdiv = 0x1,
166 		/* KPLL @600MHz */
167 		.kpll_mdiv = 0x190,
168 		.kpll_pdiv = 0x4,
169 		.kpll_sdiv = 0x2,
170 		/* DPLL @600MHz */
171 		.dpll_mdiv = 0x190,
172 		.dpll_pdiv = 0x4,
173 		.dpll_sdiv = 0x2,
174 		/* IPLL @370MHz */
175 		.ipll_mdiv = 0xb9,
176 		.ipll_pdiv = 0x3,
177 		.ipll_sdiv = 0x2,
178 		/* SPLL @400MHz */
179 		.spll_mdiv = 0xc8,
180 		.spll_pdiv = 0x3,
181 		.spll_sdiv = 0x2,
182 		/* RPLL @141Mhz */
183 		.rpll_mdiv = 0x5E,
184 		.rpll_pdiv = 0x2,
185 		.rpll_sdiv = 0x3,
186 
187 		.direct_cmd_msr = {
188 			0x00020018, 0x00030000, 0x00010046, 0x00000d70,
189 			0x00000c70
190 		},
191 		.timing_ref = 0x000000bb,
192 		.timing_row = 0x6836650f,
193 		.timing_data = 0x3630580b,
194 		.timing_power = 0x41000a26,
195 		.phy0_dqs = 0x08080808,
196 		.phy1_dqs = 0x08080808,
197 		.phy0_dq = 0x08080808,
198 		.phy1_dq = 0x08080808,
199 		.phy0_tFS = 0x8,
200 		.phy1_tFS = 0x8,
201 		.phy0_pulld_dqs = 0xf,
202 		.phy1_pulld_dqs = 0xf,
203 
204 		.lpddr3_ctrl_phy_reset = 0x1,
205 		.ctrl_start_point = 0x10,
206 		.ctrl_inc = 0x10,
207 		.ctrl_start = 0x1,
208 		.ctrl_dll_on = 0x1,
209 		.ctrl_ref = 0x8,
210 
211 		.ctrl_force = 0x1a,
212 		.ctrl_rdlat = 0x0b,
213 		.ctrl_bstlen = 0x08,
214 
215 		.fp_resync = 0x8,
216 		.iv_size = 0x7,
217 		.dfi_init_start = 1,
218 		.aref_en = 1,
219 
220 		.rd_fetch = 0x3,
221 
222 		.zq_mode_dds = 0x7,
223 		.zq_mode_term = 0x1,
224 		.zq_mode_noterm = 1,
225 
226 		/*
227 		* Dynamic Clock: Always Running
228 		* Memory Burst length: 8
229 		* Number of chips: 1
230 		* Memory Bus width: 32 bit
231 		* Memory Type: DDR3
232 		* Additional Latancy for PLL: 0 Cycle
233 		*/
234 		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
235 			DMC_MEMCONTROL_DPWRDN_DISABLE |
236 			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
237 			DMC_MEMCONTROL_TP_DISABLE |
238 			DMC_MEMCONTROL_DSREF_DISABLE |
239 			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
240 			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
241 			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
242 			DMC_MEMCONTROL_NUM_CHIP_1 |
243 			DMC_MEMCONTROL_BL_8 |
244 			DMC_MEMCONTROL_PZQ_DISABLE |
245 			DMC_MEMCONTROL_MRR_BYTE_7_0,
246 		.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
247 			DMC_MEMCONFIGX_CHIP_COL_10 |
248 			DMC_MEMCONFIGX_CHIP_ROW_15 |
249 			DMC_MEMCONFIGX_CHIP_BANK_8,
250 		.prechconfig_tp_cnt = 0xff,
251 		.dpwrdn_cyc = 0xff,
252 		.dsref_cyc = 0xffff,
253 		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
254 			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
255 			DMC_CONCONTROL_RD_FETCH_DISABLE |
256 			DMC_CONCONTROL_EMPTY_DISABLE |
257 			DMC_CONCONTROL_AREF_EN_DISABLE |
258 			DMC_CONCONTROL_IO_PD_CON_DISABLE,
259 		.dmc_channels = 1,
260 		.chips_per_channel = 1,
261 		.chips_to_configure = 1,
262 		.send_zq_init = 1,
263 		.gate_leveling_enable = 1,
264 		.read_leveling_enable = 0,
265 	}
266 #else
267 	{
268 		.mem_manuf = MEM_MANUF_ELPIDA,
269 		.mem_type = DDR_MODE_DDR3,
270 		.frequency_mhz = 800,
271 		.mpll_mdiv = 0xc8,
272 		.mpll_pdiv = 0x3,
273 		.mpll_sdiv = 0x0,
274 		.cpll_mdiv = 0xde,
275 		.cpll_pdiv = 0x4,
276 		.cpll_sdiv = 0x2,
277 		.gpll_mdiv = 0x215,
278 		.gpll_pdiv = 0xc,
279 		.gpll_sdiv = 0x1,
280 		.epll_mdiv = 0x60,
281 		.epll_pdiv = 0x3,
282 		.epll_sdiv = 0x3,
283 		.vpll_mdiv = 0x96,
284 		.vpll_pdiv = 0x3,
285 		.vpll_sdiv = 0x2,
286 
287 		.bpll_mdiv = 0x64,
288 		.bpll_pdiv = 0x3,
289 		.bpll_sdiv = 0x0,
290 		.pclk_cdrex_ratio = 0x5,
291 		.direct_cmd_msr = {
292 			0x00020018, 0x00030000, 0x00010042, 0x00000d70
293 		},
294 		.timing_ref = 0x000000bb,
295 		.timing_row = 0x8c36650e,
296 		.timing_data = 0x3630580b,
297 		.timing_power = 0x41000a44,
298 		.phy0_dqs = 0x08080808,
299 		.phy1_dqs = 0x08080808,
300 		.phy0_dq = 0x08080808,
301 		.phy1_dq = 0x08080808,
302 		.phy0_tFS = 0x4,
303 		.phy1_tFS = 0x4,
304 		.phy0_pulld_dqs = 0xf,
305 		.phy1_pulld_dqs = 0xf,
306 
307 		.lpddr3_ctrl_phy_reset = 0x1,
308 		.ctrl_start_point = 0x10,
309 		.ctrl_inc = 0x10,
310 		.ctrl_start = 0x1,
311 		.ctrl_dll_on = 0x1,
312 		.ctrl_ref = 0x8,
313 
314 		.ctrl_force = 0x1a,
315 		.ctrl_rdlat = 0x0b,
316 		.ctrl_bstlen = 0x08,
317 
318 		.fp_resync = 0x8,
319 		.iv_size = 0x7,
320 		.dfi_init_start = 1,
321 		.aref_en = 1,
322 
323 		.rd_fetch = 0x3,
324 
325 		.zq_mode_dds = 0x7,
326 		.zq_mode_term = 0x1,
327 		.zq_mode_noterm = 0,
328 
329 		/*
330 		* Dynamic Clock: Always Running
331 		* Memory Burst length: 8
332 		* Number of chips: 1
333 		* Memory Bus width: 32 bit
334 		* Memory Type: DDR3
335 		* Additional Latancy for PLL: 0 Cycle
336 		*/
337 		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
338 			DMC_MEMCONTROL_DPWRDN_DISABLE |
339 			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
340 			DMC_MEMCONTROL_TP_DISABLE |
341 			DMC_MEMCONTROL_DSREF_ENABLE |
342 			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
343 			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
344 			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
345 			DMC_MEMCONTROL_NUM_CHIP_1 |
346 			DMC_MEMCONTROL_BL_8 |
347 			DMC_MEMCONTROL_PZQ_DISABLE |
348 			DMC_MEMCONTROL_MRR_BYTE_7_0,
349 		.memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
350 			DMC_MEMCONFIGX_CHIP_COL_10 |
351 			DMC_MEMCONFIGX_CHIP_ROW_15 |
352 			DMC_MEMCONFIGX_CHIP_BANK_8,
353 		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
354 		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
355 		.prechconfig_tp_cnt = 0xff,
356 		.dpwrdn_cyc = 0xff,
357 		.dsref_cyc = 0xffff,
358 		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
359 			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
360 			DMC_CONCONTROL_RD_FETCH_DISABLE |
361 			DMC_CONCONTROL_EMPTY_DISABLE |
362 			DMC_CONCONTROL_AREF_EN_DISABLE |
363 			DMC_CONCONTROL_IO_PD_CON_DISABLE,
364 		.dmc_channels = 2,
365 		.chips_per_channel = 2,
366 		.chips_to_configure = 1,
367 		.send_zq_init = 1,
368 		.impedance = IMP_OUTPUT_DRV_30_OHM,
369 		.gate_leveling_enable = 0,
370 	}, {
371 		.mem_manuf = MEM_MANUF_SAMSUNG,
372 		.mem_type = DDR_MODE_DDR3,
373 		.frequency_mhz = 800,
374 		.mpll_mdiv = 0xc8,
375 		.mpll_pdiv = 0x3,
376 		.mpll_sdiv = 0x0,
377 		.cpll_mdiv = 0xde,
378 		.cpll_pdiv = 0x4,
379 		.cpll_sdiv = 0x2,
380 		.gpll_mdiv = 0x215,
381 		.gpll_pdiv = 0xc,
382 		.gpll_sdiv = 0x1,
383 		.epll_mdiv = 0x60,
384 		.epll_pdiv = 0x3,
385 		.epll_sdiv = 0x3,
386 		.vpll_mdiv = 0x96,
387 		.vpll_pdiv = 0x3,
388 		.vpll_sdiv = 0x2,
389 
390 		.bpll_mdiv = 0x64,
391 		.bpll_pdiv = 0x3,
392 		.bpll_sdiv = 0x0,
393 		.pclk_cdrex_ratio = 0x5,
394 		.direct_cmd_msr = {
395 			0x00020018, 0x00030000, 0x00010000, 0x00000d70
396 		},
397 		.timing_ref = 0x000000bb,
398 		.timing_row = 0x8c36650e,
399 		.timing_data = 0x3630580b,
400 		.timing_power = 0x41000a44,
401 		.phy0_dqs = 0x08080808,
402 		.phy1_dqs = 0x08080808,
403 		.phy0_dq = 0x08080808,
404 		.phy1_dq = 0x08080808,
405 		.phy0_tFS = 0x8,
406 		.phy1_tFS = 0x8,
407 		.phy0_pulld_dqs = 0xf,
408 		.phy1_pulld_dqs = 0xf,
409 
410 		.lpddr3_ctrl_phy_reset = 0x1,
411 		.ctrl_start_point = 0x10,
412 		.ctrl_inc = 0x10,
413 		.ctrl_start = 0x1,
414 		.ctrl_dll_on = 0x1,
415 		.ctrl_ref = 0x8,
416 
417 		.ctrl_force = 0x1a,
418 		.ctrl_rdlat = 0x0b,
419 		.ctrl_bstlen = 0x08,
420 
421 		.fp_resync = 0x8,
422 		.iv_size = 0x7,
423 		.dfi_init_start = 1,
424 		.aref_en = 1,
425 
426 		.rd_fetch = 0x3,
427 
428 		.zq_mode_dds = 0x5,
429 		.zq_mode_term = 0x1,
430 		.zq_mode_noterm = 1,
431 
432 		/*
433 		* Dynamic Clock: Always Running
434 		* Memory Burst length: 8
435 		* Number of chips: 1
436 		* Memory Bus width: 32 bit
437 		* Memory Type: DDR3
438 		* Additional Latancy for PLL: 0 Cycle
439 		*/
440 		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
441 			DMC_MEMCONTROL_DPWRDN_DISABLE |
442 			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
443 			DMC_MEMCONTROL_TP_DISABLE |
444 			DMC_MEMCONTROL_DSREF_ENABLE |
445 			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
446 			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
447 			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
448 			DMC_MEMCONTROL_NUM_CHIP_1 |
449 			DMC_MEMCONTROL_BL_8 |
450 			DMC_MEMCONTROL_PZQ_DISABLE |
451 			DMC_MEMCONTROL_MRR_BYTE_7_0,
452 		.memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
453 			DMC_MEMCONFIGX_CHIP_COL_10 |
454 			DMC_MEMCONFIGX_CHIP_ROW_15 |
455 			DMC_MEMCONFIGX_CHIP_BANK_8,
456 		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
457 		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
458 		.prechconfig_tp_cnt = 0xff,
459 		.dpwrdn_cyc = 0xff,
460 		.dsref_cyc = 0xffff,
461 		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
462 			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
463 			DMC_CONCONTROL_RD_FETCH_DISABLE |
464 			DMC_CONCONTROL_EMPTY_DISABLE |
465 			DMC_CONCONTROL_AREF_EN_DISABLE |
466 			DMC_CONCONTROL_IO_PD_CON_DISABLE,
467 		.dmc_channels = 2,
468 		.chips_per_channel = 2,
469 		.chips_to_configure = 1,
470 		.send_zq_init = 1,
471 		.impedance = IMP_OUTPUT_DRV_40_OHM,
472 		.gate_leveling_enable = 1,
473 	}
474 #endif
475 };
476 
477 /**
478  * Get the required memory type and speed (SPL version).
479  *
480  * In SPL we have no device tree, so we use the machine parameters
481  *
482  * @param mem_type	Returns memory type
483  * @param frequency_mhz	Returns memory speed in MHz
484  * @param arm_freq	Returns ARM clock speed in MHz
485  * @param mem_manuf	Return Memory Manufacturer name
486  */
487 static void clock_get_mem_selection(enum ddr_mode *mem_type,
488 		unsigned *frequency_mhz, unsigned *arm_freq,
489 		enum mem_manuf *mem_manuf)
490 {
491 	struct spl_machine_param *params;
492 
493 	params = spl_get_machine_params();
494 	*mem_type = params->mem_type;
495 	*frequency_mhz = params->frequency_mhz;
496 	*arm_freq = params->arm_freq_mhz;
497 	*mem_manuf = params->mem_manuf;
498 }
499 
500 /* Get the ratios for setting ARM clock */
501 struct arm_clk_ratios *get_arm_ratios(void)
502 {
503 	struct arm_clk_ratios *arm_ratio;
504 	enum ddr_mode mem_type;
505 	enum mem_manuf mem_manuf;
506 	unsigned frequency_mhz, arm_freq;
507 	int i;
508 
509 	clock_get_mem_selection(&mem_type, &frequency_mhz,
510 				&arm_freq, &mem_manuf);
511 
512 	for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
513 		i++, arm_ratio++) {
514 		if (arm_ratio->arm_freq_mhz == arm_freq)
515 			return arm_ratio;
516 	}
517 
518 	/* will hang if failed to find clock ratio */
519 	while (1)
520 		;
521 
522 	return NULL;
523 }
524 
525 struct mem_timings *clock_get_mem_timings(void)
526 {
527 	struct mem_timings *mem;
528 	enum ddr_mode mem_type;
529 	enum mem_manuf mem_manuf;
530 	unsigned frequency_mhz, arm_freq;
531 	int i;
532 
533 	clock_get_mem_selection(&mem_type, &frequency_mhz,
534 				&arm_freq, &mem_manuf);
535 	for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
536 	     i++, mem++) {
537 		if (mem->mem_type == mem_type &&
538 		    mem->frequency_mhz == frequency_mhz &&
539 		    mem->mem_manuf == mem_manuf)
540 			return mem;
541 	}
542 
543 	/* will hang if failed to find memory timings */
544 	while (1)
545 		;
546 
547 	return NULL;
548 }
549 
550 static void exynos5250_system_clock_init(void)
551 {
552 	struct exynos5_clock *clk =
553 		(struct exynos5_clock *)samsung_get_base_clock();
554 	struct mem_timings *mem;
555 	struct arm_clk_ratios *arm_clk_ratio;
556 	u32 val, tmp;
557 
558 	mem = clock_get_mem_timings();
559 	arm_clk_ratio = get_arm_ratios();
560 
561 	clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
562 	do {
563 		val = readl(&clk->mux_stat_cpu);
564 	} while ((val | MUX_APLL_SEL_MASK) != val);
565 
566 	clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
567 	do {
568 		val = readl(&clk->mux_stat_core1);
569 	} while ((val | MUX_MPLL_SEL_MASK) != val);
570 
571 	clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
572 	clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
573 	clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
574 	clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
575 	tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
576 		| MUX_GPLL_SEL_MASK;
577 	do {
578 		val = readl(&clk->mux_stat_top2);
579 	} while ((val | tmp) != val);
580 
581 	clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
582 	do {
583 		val = readl(&clk->mux_stat_cdrex);
584 	} while ((val | MUX_BPLL_SEL_MASK) != val);
585 
586 	/* PLL locktime */
587 	writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
588 	writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
589 	writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
590 	writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
591 	writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
592 	writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
593 	writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
594 
595 	writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
596 
597 	writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
598 	do {
599 		val = readl(&clk->mux_stat_cpu);
600 	} while ((val | HPM_SEL_SCLK_MPLL) != val);
601 
602 	val = arm_clk_ratio->arm2_ratio << 28
603 		| arm_clk_ratio->apll_ratio << 24
604 		| arm_clk_ratio->pclk_dbg_ratio << 20
605 		| arm_clk_ratio->atb_ratio << 16
606 		| arm_clk_ratio->periph_ratio << 12
607 		| arm_clk_ratio->acp_ratio << 8
608 		| arm_clk_ratio->cpud_ratio << 4
609 		| arm_clk_ratio->arm_ratio;
610 	writel(val, &clk->div_cpu0);
611 	do {
612 		val = readl(&clk->div_stat_cpu0);
613 	} while (0 != val);
614 
615 	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
616 	do {
617 		val = readl(&clk->div_stat_cpu1);
618 	} while (0 != val);
619 
620 	/* Set APLL */
621 	writel(APLL_CON1_VAL, &clk->apll_con1);
622 	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
623 			arm_clk_ratio->apll_sdiv);
624 	writel(val, &clk->apll_con0);
625 	while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
626 		;
627 
628 	/* Set MPLL */
629 	writel(MPLL_CON1_VAL, &clk->mpll_con1);
630 	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
631 	writel(val, &clk->mpll_con0);
632 	while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
633 		;
634 
635 	/* Set BPLL */
636 	writel(BPLL_CON1_VAL, &clk->bpll_con1);
637 	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
638 	writel(val, &clk->bpll_con0);
639 	while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
640 		;
641 
642 	/* Set CPLL */
643 	writel(CPLL_CON1_VAL, &clk->cpll_con1);
644 	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
645 	writel(val, &clk->cpll_con0);
646 	while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
647 		;
648 
649 	/* Set GPLL */
650 	writel(GPLL_CON1_VAL, &clk->gpll_con1);
651 	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
652 	writel(val, &clk->gpll_con0);
653 	while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
654 		;
655 
656 	/* Set EPLL */
657 	writel(EPLL_CON2_VAL, &clk->epll_con2);
658 	writel(EPLL_CON1_VAL, &clk->epll_con1);
659 	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
660 	writel(val, &clk->epll_con0);
661 	while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
662 		;
663 
664 	/* Set VPLL */
665 	writel(VPLL_CON2_VAL, &clk->vpll_con2);
666 	writel(VPLL_CON1_VAL, &clk->vpll_con1);
667 	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
668 	writel(val, &clk->vpll_con0);
669 	while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
670 		;
671 
672 	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
673 	writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
674 	while (readl(&clk->div_stat_core0) != 0)
675 		;
676 
677 	writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
678 	while (readl(&clk->div_stat_core1) != 0)
679 		;
680 
681 	writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
682 	while (readl(&clk->div_stat_sysrgt) != 0)
683 		;
684 
685 	writel(CLK_DIV_ACP_VAL, &clk->div_acp);
686 	while (readl(&clk->div_stat_acp) != 0)
687 		;
688 
689 	writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
690 	while (readl(&clk->div_stat_syslft) != 0)
691 		;
692 
693 	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
694 	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
695 	writel(TOP2_VAL, &clk->src_top2);
696 	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
697 
698 	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
699 	while (readl(&clk->div_stat_top0))
700 		;
701 
702 	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
703 	while (readl(&clk->div_stat_top1))
704 		;
705 
706 	writel(CLK_SRC_LEX_VAL, &clk->src_lex);
707 	while (1) {
708 		val = readl(&clk->mux_stat_lex);
709 		if (val == (val | 1))
710 			break;
711 	}
712 
713 	writel(CLK_DIV_LEX_VAL, &clk->div_lex);
714 	while (readl(&clk->div_stat_lex))
715 		;
716 
717 	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
718 	while (readl(&clk->div_stat_r0x))
719 		;
720 
721 	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
722 	while (readl(&clk->div_stat_r0x))
723 		;
724 
725 	writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
726 	while (readl(&clk->div_stat_r1x))
727 		;
728 
729 	writel(CLK_REG_DISABLE, &clk->src_cdrex);
730 
731 	writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
732 	while (readl(&clk->div_stat_cdrex))
733 		;
734 
735 	val = readl(&clk->src_cpu);
736 	val |= CLK_SRC_CPU_VAL;
737 	writel(val, &clk->src_cpu);
738 
739 	val = readl(&clk->src_top2);
740 	val |= CLK_SRC_TOP2_VAL;
741 	writel(val, &clk->src_top2);
742 
743 	val = readl(&clk->src_core1);
744 	val |= CLK_SRC_CORE1_VAL;
745 	writel(val, &clk->src_core1);
746 
747 	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
748 	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
749 	while (readl(&clk->div_stat_fsys0))
750 		;
751 
752 	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
753 	writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
754 	writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
755 	writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
756 	writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
757 	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
758 	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
759 	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
760 
761 	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
762 	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
763 
764 	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
765 	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
766 	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
767 	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
768 
769 	writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
770 	writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
771 	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
772 	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
773 	writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
774 
775 	/* FIMD1 SRC CLK SELECTION */
776 	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
777 
778 	val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
779 		| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
780 		| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
781 		| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
782 	writel(val, &clk->div_fsys2);
783 }
784 
785 static void exynos5420_system_clock_init(void)
786 {
787 	struct exynos5420_clock *clk =
788 		(struct exynos5420_clock *)samsung_get_base_clock();
789 	struct mem_timings *mem;
790 	struct arm_clk_ratios *arm_clk_ratio;
791 	u32 val;
792 
793 	mem = clock_get_mem_timings();
794 	arm_clk_ratio = get_arm_ratios();
795 
796 	/* PLL locktime */
797 	writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
798 	writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
799 	writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
800 	writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
801 	writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
802 	writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
803 	writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
804 	writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
805 	writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
806 	writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
807 	writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
808 
809 	setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
810 
811 	writel(0, &clk->src_top6);
812 
813 	writel(0, &clk->src_cdrex);
814 	writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
815 	writel(HPM_RATIO,  &clk->div_cpu1);
816 	writel(CLK_DIV_CPU0_VAL,  &clk->div_cpu0);
817 
818 	/* switch A15 clock source to OSC clock before changing APLL */
819 	clrbits_le32(&clk->src_cpu, APLL_FOUT);
820 
821 	/* Set APLL */
822 	writel(APLL_CON1_VAL, &clk->apll_con1);
823 	val = set_pll(arm_clk_ratio->apll_mdiv,
824 		      arm_clk_ratio->apll_pdiv,
825 		      arm_clk_ratio->apll_sdiv);
826 	writel(val, &clk->apll_con0);
827 	while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
828 		;
829 
830 	/* now it is safe to switch to APLL */
831 	setbits_le32(&clk->src_cpu, APLL_FOUT);
832 
833 	writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
834 	writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
835 
836 	/* switch A7 clock source to OSC clock before changing KPLL */
837 	clrbits_le32(&clk->src_kfc, KPLL_FOUT);
838 
839 	/* Set KPLL*/
840 	writel(KPLL_CON1_VAL, &clk->kpll_con1);
841 	val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
842 	writel(val, &clk->kpll_con0);
843 	while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
844 		;
845 
846 	/* now it is safe to switch to KPLL */
847 	setbits_le32(&clk->src_kfc, KPLL_FOUT);
848 
849 	/* Set MPLL */
850 	writel(MPLL_CON1_VAL, &clk->mpll_con1);
851 	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
852 	writel(val, &clk->mpll_con0);
853 	while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
854 		;
855 
856 	/* Set DPLL */
857 	writel(DPLL_CON1_VAL, &clk->dpll_con1);
858 	val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
859 	writel(val, &clk->dpll_con0);
860 	while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
861 		;
862 
863 	/* Set EPLL */
864 	writel(EPLL_CON2_VAL, &clk->epll_con2);
865 	writel(EPLL_CON1_VAL, &clk->epll_con1);
866 	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
867 	writel(val, &clk->epll_con0);
868 	while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
869 		;
870 
871 	/* Set CPLL */
872 	writel(CPLL_CON1_VAL, &clk->cpll_con1);
873 	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
874 	writel(val, &clk->cpll_con0);
875 	while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
876 		;
877 
878 	/* Set IPLL */
879 	writel(IPLL_CON1_VAL, &clk->ipll_con1);
880 	val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
881 	writel(val, &clk->ipll_con0);
882 	while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
883 		;
884 
885 	/* Set VPLL */
886 	writel(VPLL_CON1_VAL, &clk->vpll_con1);
887 	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
888 	writel(val, &clk->vpll_con0);
889 	while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
890 		;
891 
892 	/* Set BPLL */
893 	writel(BPLL_CON1_VAL, &clk->bpll_con1);
894 	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
895 	writel(val, &clk->bpll_con0);
896 	while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
897 		;
898 
899 	/* Set SPLL */
900 	writel(SPLL_CON1_VAL, &clk->spll_con1);
901 	val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
902 	writel(val, &clk->spll_con0);
903 	while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
904 		;
905 
906 	/* Set RPLL */
907 	writel(RPLL_CON2_VAL, &clk->rpll_con2);
908 	writel(RPLL_CON1_VAL, &clk->rpll_con1);
909 	val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
910 	writel(val, &clk->rpll_con0);
911 	while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
912 		;
913 
914 	writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
915 	writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
916 
917 	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
918 	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
919 	writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
920 	writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
921 
922 	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
923 	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
924 	writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
925 
926 	writel(0, &clk->src_top10);
927 	writel(0, &clk->src_top11);
928 	writel(0, &clk->src_top12);
929 
930 	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
931 	writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
932 	writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
933 
934 	/* DISP1 BLK CLK SELECTION */
935 	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
936 	writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
937 
938 	/* AUDIO BLK */
939 	writel(AUDIO0_SEL_EPLL, &clk->src_mau);
940 	writel(DIV_MAU_VAL, &clk->div_mau);
941 
942 	/* FSYS */
943 	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
944 	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
945 	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
946 	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
947 
948 	writel(CLK_SRC_ISP_VAL, &clk->src_isp);
949 	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
950 	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
951 
952 	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
953 	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
954 
955 	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
956 	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
957 	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
958 	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
959 	writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
960 
961 	writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
962 
963 	writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
964 	writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
965 	writel(CLK_DIV_G2D, &clk->div_g2d);
966 
967 	writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
968 	writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
969 	writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
970 }
971 
972 void system_clock_init(void)
973 {
974 	if (proid_is_exynos5420() || proid_is_exynos5800())
975 		exynos5420_system_clock_init();
976 	else
977 		exynos5250_system_clock_init();
978 }
979 
980 void clock_init_dp_clock(void)
981 {
982 	struct exynos5_clock *clk =
983 		(struct exynos5_clock *)samsung_get_base_clock();
984 
985 	/* DP clock enable */
986 	setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
987 
988 	/* We run DP at 267 Mhz */
989 	setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
990 }
991 
992 /*
993  * Set clock divisor value for booting from EMMC.
994  * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
995  */
996 void emmc_boot_clk_div_set(void)
997 {
998 	struct exynos5_clock *clk =
999 		(struct exynos5_clock *)samsung_get_base_clock();
1000 	unsigned int div_mmc;
1001 
1002 	div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
1003 	div_mmc |= FSYS1_MMC0_DIV_VAL;
1004 	writel(div_mmc, (unsigned int) &clk->div_fsys1);
1005 }
1006