1 /* 2 * Power and Sleep Controller (PSC) functions. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * Copyright (C) 2008 Lyrtech <www.lyrtech.com> 6 * Copyright (C) 2004 Texas Instruments. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/io.h> 14 15 /* 16 * The PSC manages three inputs to a "module" which may be a peripheral or 17 * CPU. Those inputs are the module's: clock; reset signal; and sometimes 18 * its power domain. For our purposes, we only care whether clock and power 19 * are active, and the module is out of reset. 20 * 21 * DaVinci chips may include two separate power domains: "Always On" and "DSP". 22 * Chips without a DSP generally have only one domain. 23 * 24 * The "Always On" power domain is always on when the chip is on, and is 25 * powered by the VDD pins (on DM644X). The majority of DaVinci modules 26 * lie within the "Always On" power domain. 27 * 28 * A separate domain called the "DSP" domain houses the C64x+ and other video 29 * hardware such as VICP. In some chips, the "DSP" domain is not always on. 30 * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X). 31 */ 32 33 /* Works on Always On power domain only (no PD argument) */ 34 static void lpsc_transition(unsigned int id, unsigned int state) 35 { 36 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 37 #ifdef CONFIG_SOC_DA8XX 38 struct davinci_psc_regs *psc_regs; 39 #endif 40 41 #ifndef CONFIG_SOC_DA8XX 42 if (id >= DAVINCI_LPSC_GEM) 43 return; /* Don't work on DSP Power Domain */ 44 45 mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); 46 mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); 47 ptstat = REG_P(PSC_PTSTAT); 48 ptcmd = REG_P(PSC_PTCMD); 49 #else 50 if (id < DAVINCI_LPSC_PSC1_BASE) { 51 if (id >= PSC_PSC0_MODULE_ID_CNT) 52 return; 53 psc_regs = davinci_psc0_regs; 54 mdstat = &psc_regs->psc0.mdstat[id]; 55 mdctl = &psc_regs->psc0.mdctl[id]; 56 } else { 57 id -= DAVINCI_LPSC_PSC1_BASE; 58 if (id >= PSC_PSC1_MODULE_ID_CNT) 59 return; 60 psc_regs = davinci_psc1_regs; 61 mdstat = &psc_regs->psc1.mdstat[id]; 62 mdctl = &psc_regs->psc1.mdctl[id]; 63 } 64 ptstat = &psc_regs->ptstat; 65 ptcmd = &psc_regs->ptcmd; 66 #endif 67 68 while (readl(ptstat) & 0x01) 69 continue; 70 71 if ((readl(mdstat) & PSC_MDSTAT_STATE) == state) 72 return; /* Already in that state */ 73 74 writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl); 75 76 switch (id) { 77 #ifdef CONFIG_SOC_DM644X 78 /* Special treatment for some modules as for sprue14 p.7.4.2 */ 79 case DAVINCI_LPSC_VPSSSLV: 80 case DAVINCI_LPSC_EMAC: 81 case DAVINCI_LPSC_EMAC_WRAPPER: 82 case DAVINCI_LPSC_MDIO: 83 case DAVINCI_LPSC_USB: 84 case DAVINCI_LPSC_ATA: 85 case DAVINCI_LPSC_VLYNQ: 86 case DAVINCI_LPSC_UHPI: 87 case DAVINCI_LPSC_DDR_EMIF: 88 case DAVINCI_LPSC_AEMIF: 89 case DAVINCI_LPSC_MMC_SD: 90 case DAVINCI_LPSC_MEMSTICK: 91 case DAVINCI_LPSC_McBSP: 92 case DAVINCI_LPSC_GPIO: 93 writel(readl(mdctl) | 0x200, mdctl); 94 break; 95 #endif 96 } 97 98 writel(0x01, ptcmd); 99 100 while (readl(ptstat) & 0x01) 101 continue; 102 while ((readl(mdstat) & PSC_MDSTAT_STATE) != state) 103 continue; 104 } 105 106 void lpsc_on(unsigned int id) 107 { 108 lpsc_transition(id, 0x03); 109 } 110 111 void lpsc_syncreset(unsigned int id) 112 { 113 lpsc_transition(id, 0x01); 114 } 115 116 void lpsc_disable(unsigned int id) 117 { 118 lpsc_transition(id, 0x0); 119 } 120 121 /* Not all DaVinci chips have a DSP power domain. */ 122 #ifdef CONFIG_SOC_DM644X 123 124 /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ 125 #if !defined(CONFIG_SYS_USE_DSPLINK) 126 void dsp_on(void) 127 { 128 int i; 129 130 if (REG(PSC_PDSTAT1) & 0x1f) 131 return; /* Already on */ 132 133 REG(PSC_GBLCTL) |= 0x01; 134 REG(PSC_PDCTL1) |= 0x01; 135 REG(PSC_PDCTL1) &= ~0x100; 136 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; 137 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; 138 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; 139 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; 140 REG(PSC_PTCMD) = 0x02; 141 142 for (i = 0; i < 100; i++) { 143 if (REG(PSC_EPCPR) & 0x02) 144 break; 145 } 146 147 REG(PSC_CHP_SHRTSW) = 0x01; 148 REG(PSC_PDCTL1) |= 0x100; 149 REG(PSC_EPCCR) = 0x02; 150 151 for (i = 0; i < 100; i++) { 152 if (!(REG(PSC_PTSTAT) & 0x02)) 153 break; 154 } 155 156 REG(PSC_GBLCTL) &= ~0x1f; 157 } 158 #endif /* CONFIG_SYS_USE_DSPLINK */ 159 160 #endif /* have a DSP */ 161