1/*
2 * Low-level board setup code for TI DaVinci SoC based boards.
3 *
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 *
6 * Partially based on TI sources, original copyrights follow:
7 */
8
9/*
10 * Board specific setup info
11 *
12 * (C) Copyright 2003
13 * Texas Instruments, <www.ti.com>
14 * Kshitij Gupta <Kshitij@ti.com>
15 *
16 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
17 *
18 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
19 *
20 * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
21 *
22 * Modified for DV-EVM board by Swaminathan S, Nov 2005
23 *
24 * SPDX-License-Identifier:	GPL-2.0+
25 */
26
27#include <config.h>
28
29#define MDSTAT_STATE	0x3f
30
31.globl	lowlevel_init
32lowlevel_init:
33#ifdef CONFIG_SOC_DM644X
34
35	/*-------------------------------------------------------*
36	 * Mask all IRQs by setting all bits in the EINT default *
37	 *-------------------------------------------------------*/
38	mov	r1, $0
39	ldr	r0, =EINT_ENABLE0
40	str	r1, [r0]
41	ldr	r0, =EINT_ENABLE1
42	str	r1, [r0]
43
44	/*------------------------------------------------------*
45	 * Put the GEM in reset					*
46	 *------------------------------------------------------*/
47
48	/* Put the GEM in reset */
49	ldr	r8, PSC_GEM_FLAG_CLEAR
50	ldr	r6, MDCTL_GEM
51	ldr	r7, [r6]
52	and	r7, r7, r8
53	str	r7, [r6]
54
55	/* Enable the Power Domain Transition Command */
56	ldr	r6, PTCMD
57	ldr	r7, [r6]
58	orr	r7, r7, $0x02
59	str	r7, [r6]
60
61	/* Check for Transition Complete(PTSTAT) */
62checkStatClkStopGem:
63	ldr	r6, PTSTAT
64	ldr	r7, [r6]
65	ands	r7, r7, $0x02
66	bne	checkStatClkStopGem
67
68	/* Check for GEM Reset Completion */
69checkGemStatClkStop:
70	ldr	r6, MDSTAT_GEM
71	ldr	r7, [r6]
72	ands	r7, r7, $0x100
73	bne	checkGemStatClkStop
74
75	/* Do this for enabling a WDT initiated reset this is a workaround
76	   for a chip bug.  Not required under normal situations */
77	ldr	r6, P1394
78	mov	r10, $0
79	str	r10, [r6]
80
81	/*------------------------------------------------------*
82	 * Enable L1 & L2 Memories in Fast mode                 *
83	 *------------------------------------------------------*/
84	ldr	r6, DFT_ENABLE
85	mov	r10, $0x01
86	str	r10, [r6]
87
88	ldr	r6, MMARG_BRF0
89	ldr	r10, MMARG_BRF0_VAL
90	str	r10, [r6]
91
92	ldr	r6, DFT_ENABLE
93	mov	r10, $0
94	str	r10, [r6]
95
96	/*------------------------------------------------------*
97	 * DDR2 PLL Initialization				*
98	 *------------------------------------------------------*/
99
100	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
101	mov	r10, $0
102	ldr	r6, PLL2_CTL
103	ldr	r7, PLL_CLKSRC_MASK
104	ldr	r8, [r6]
105	and	r8, r8, r7
106	mov	r9, r10, lsl $8
107	orr	r8, r8, r9
108	str	r8, [r6]
109
110	/* Select the PLLEN source */
111	ldr	r7, PLL_ENSRC_MASK
112	and	r8, r8, r7
113	str	r8, [r6]
114
115	/* Bypass the PLL */
116	ldr	r7, PLL_BYPASS_MASK
117	and	r8, r8, r7
118	str	r8, [r6]
119
120	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
121	mov	r10, $0x20
122WaitPPL2Loop:
123	subs	r10, r10, $1
124	bne	WaitPPL2Loop
125
126	/* Reset the PLL */
127	ldr	r7, PLL_RESET_MASK
128	and	r8, r8, r7
129	str	r8, [r6]
130
131	/* Power up the PLL */
132	ldr	r7, PLL_PWRUP_MASK
133	and	r8, r8, r7
134	str	r8, [r6]
135
136	/* Enable the PLL from Disable Mode */
137	ldr	r7, PLL_DISABLE_ENABLE_MASK
138	and	r8, r8, r7
139	str	r8, [r6]
140
141	/* Program the PLL Multiplier */
142	ldr	r6, PLL2_PLLM
143	mov	r2, $0x17	/* 162 MHz */
144	str	r2, [r6]
145
146	/* Program the PLL2 Divisor Value */
147	ldr	r6, PLL2_DIV2
148	mov	r3, $0x01
149	str	r3, [r6]
150
151	/* Program the PLL2 Divisor Value */
152	ldr	r6, PLL2_DIV1
153	mov	r4, $0x0b	/* 54 MHz */
154	str	r4, [r6]
155
156	/* PLL2 DIV2 MMR */
157	ldr	r8, PLL2_DIV_MASK
158	ldr	r6, PLL2_DIV2
159	ldr	r9, [r6]
160	and	r8, r8, r9
161	mov	r9, $0x01
162	mov	r9, r9, lsl $15
163	orr	r8, r8, r9
164	str	r8, [r6]
165
166	/* Program the GOSET bit to take new divider values */
167	ldr	r6, PLL2_PLLCMD
168	ldr	r7, [r6]
169	orr	r7, r7, $0x01
170	str	r7, [r6]
171
172	/* Wait for Done */
173	ldr	r6, PLL2_PLLSTAT
174doneLoop_0:
175	ldr	r7, [r6]
176	ands	r7, r7, $0x01
177	bne	doneLoop_0
178
179	/* PLL2 DIV1 MMR */
180	ldr	r8, PLL2_DIV_MASK
181	ldr	r6, PLL2_DIV1
182	ldr	r9, [r6]
183	and	r8, r8, r9
184	mov	r9, $0x01
185	mov	r9, r9, lsl $15
186	orr	r8, r8, r9
187	str	r8, [r6]
188
189	/* Program the GOSET bit to take new divider values */
190	ldr	r6, PLL2_PLLCMD
191	ldr	r7, [r6]
192	orr	r7, r7, $0x01
193	str	r7, [r6]
194
195	/* Wait for Done */
196	ldr	r6, PLL2_PLLSTAT
197doneLoop:
198	ldr	r7, [r6]
199	ands	r7, r7, $0x01
200	bne	doneLoop
201
202	/* Wait for PLL to Reset Properly */
203	mov	r10, $0x218
204ResetPPL2Loop:
205	subs	r10, r10, $1
206	bne	ResetPPL2Loop
207
208	/* Bring PLL out of Reset */
209	ldr	r6, PLL2_CTL
210	ldr	r8, [r6]
211	orr	r8, r8, $0x08
212	str	r8, [r6]
213
214	/* Wait for PLL to Lock */
215	ldr	r10, PLL_LOCK_COUNT
216PLL2Lock:
217	subs	r10, r10, $1
218	bne	PLL2Lock
219
220	/* Enable the PLL */
221	ldr	r6, PLL2_CTL
222	ldr	r8, [r6]
223	orr	r8, r8, $0x01
224	str	r8, [r6]
225
226	/*------------------------------------------------------*
227	 * Issue Soft Reset to DDR Module			*
228	 *------------------------------------------------------*/
229
230	/* Shut down the DDR2 LPSC Module */
231	ldr	r8, PSC_FLAG_CLEAR
232	ldr	r6, MDCTL_DDR2
233	ldr	r7, [r6]
234	and	r7, r7, r8
235	orr	r7, r7, $0x03
236	str	r7, [r6]
237
238	/* Enable the Power Domain Transition Command */
239	ldr	r6, PTCMD
240	ldr	r7, [r6]
241	orr	r7, r7, $0x01
242	str	r7, [r6]
243
244	/* Check for Transition Complete(PTSTAT) */
245checkStatClkStop:
246	ldr	r6, PTSTAT
247	ldr	r7, [r6]
248	ands	r7, r7, $0x01
249	bne	checkStatClkStop
250
251	/* Check for DDR2 Controller Enable Completion */
252checkDDRStatClkStop:
253	ldr	r6, MDSTAT_DDR2
254	ldr	r7, [r6]
255	and	r7, r7, $MDSTAT_STATE
256	cmp	r7, $0x03
257	bne	checkDDRStatClkStop
258
259	/*------------------------------------------------------*
260	 * Program DDR2 MMRs for 162MHz Setting			*
261	 *------------------------------------------------------*/
262
263	/* Program PHY Control Register */
264	ldr	r6, DDRCTL
265	ldr	r7, DDRCTL_VAL
266	str	r7, [r6]
267
268	/* Program SDRAM Bank Config Register */
269	ldr	r6, SDCFG
270	ldr	r7, SDCFG_VAL
271	str	r7, [r6]
272
273	/* Program SDRAM TIM-0 Config Register */
274	ldr	r6, SDTIM0
275	ldr	r7, SDTIM0_VAL_162MHz
276	str	r7, [r6]
277
278	/* Program SDRAM TIM-1 Config Register */
279	ldr	r6, SDTIM1
280	ldr	r7, SDTIM1_VAL_162MHz
281	str	r7, [r6]
282
283	/* Program the SDRAM Bank Config Control Register */
284	ldr	r10, MASK_VAL
285	ldr	r8, SDCFG
286	ldr	r9, SDCFG_VAL
287	and	r9, r9, r10
288	str	r9, [r8]
289
290	/* Program SDRAM SDREF Config Register */
291	ldr	r6, SDREF
292	ldr	r7, SDREF_VAL
293	str	r7, [r6]
294
295	/*------------------------------------------------------*
296	 * Issue Soft Reset to DDR Module			*
297	 *------------------------------------------------------*/
298
299	/* Issue a Dummy DDR2 read/write */
300	ldr	r8, DDR2_START_ADDR
301	ldr	r7, DUMMY_VAL
302	str	r7, [r8]
303	ldr	r7, [r8]
304
305	/* Shut down the DDR2 LPSC Module */
306	ldr	r8, PSC_FLAG_CLEAR
307	ldr	r6, MDCTL_DDR2
308	ldr	r7, [r6]
309	and	r7, r7, r8
310	orr	r7, r7, $0x01
311	str	r7, [r6]
312
313	/* Enable the Power Domain Transition Command */
314	ldr	r6, PTCMD
315	ldr	r7, [r6]
316	orr	r7, r7, $0x01
317	str	r7, [r6]
318
319	/* Check for Transition Complete(PTSTAT) */
320checkStatClkStop2:
321	ldr	r6, PTSTAT
322	ldr	r7, [r6]
323	ands	r7, r7, $0x01
324	bne	checkStatClkStop2
325
326	/* Check for DDR2 Controller Enable Completion */
327checkDDRStatClkStop2:
328	ldr	r6, MDSTAT_DDR2
329	ldr	r7, [r6]
330	and	r7, r7, $MDSTAT_STATE
331	cmp	r7, $0x01
332	bne	checkDDRStatClkStop2
333
334	/*------------------------------------------------------*
335	 * Turn DDR2 Controller Clocks On			*
336	 *------------------------------------------------------*/
337
338	/* Enable the DDR2 LPSC Module */
339	ldr	r6, MDCTL_DDR2
340	ldr	r7, [r6]
341	orr	r7, r7, $0x03
342	str	r7, [r6]
343
344	/* Enable the Power Domain Transition Command */
345	ldr	r6, PTCMD
346	ldr	r7, [r6]
347	orr	r7, r7, $0x01
348	str	r7, [r6]
349
350	/* Check for Transition Complete(PTSTAT) */
351checkStatClkEn2:
352	ldr	r6, PTSTAT
353	ldr	r7, [r6]
354	ands	r7, r7, $0x01
355	bne	checkStatClkEn2
356
357	/* Check for DDR2 Controller Enable Completion */
358checkDDRStatClkEn2:
359	ldr	r6, MDSTAT_DDR2
360	ldr	r7, [r6]
361	and	r7, r7, $MDSTAT_STATE
362	cmp	r7, $0x03
363	bne	checkDDRStatClkEn2
364
365	/*  DDR Writes and Reads */
366	ldr	r6, CFGTEST
367	mov	r3, $0x01
368	str	r3, [r6]
369
370	/*------------------------------------------------------*
371	 * System PLL Initialization				*
372	 *------------------------------------------------------*/
373
374	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
375	mov	r2, $0
376	ldr	r6, PLL1_CTL
377	ldr	r7, PLL_CLKSRC_MASK
378	ldr	r8, [r6]
379	and	r8, r8, r7
380	mov	r9, r2, lsl $8
381	orr	r8, r8, r9
382	str	r8, [r6]
383
384	/* Select the PLLEN source */
385	ldr	r7, PLL_ENSRC_MASK
386	and	r8, r8, r7
387	str	r8, [r6]
388
389	/* Bypass the PLL */
390	ldr	r7, PLL_BYPASS_MASK
391	and	r8, r8, r7
392	str	r8, [r6]
393
394	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
395	mov	r10, $0x20
396
397WaitLoop:
398	subs	r10, r10, $1
399	bne	WaitLoop
400
401	/* Reset the PLL */
402	ldr	r7, PLL_RESET_MASK
403	and	r8, r8, r7
404	str	r8, [r6]
405
406	/* Disable the PLL */
407	orr	r8, r8, $0x10
408	str	r8, [r6]
409
410	/* Power up the PLL */
411	ldr	r7, PLL_PWRUP_MASK
412	and	r8, r8, r7
413	str	r8, [r6]
414
415	/* Enable the PLL from Disable Mode */
416	ldr	r7, PLL_DISABLE_ENABLE_MASK
417	and	r8, r8, r7
418	str	r8, [r6]
419
420	/* Program the PLL Multiplier */
421	ldr	r6, PLL1_PLLM
422	mov	r3, $0x15	/* For 594MHz */
423	str	r3, [r6]
424
425	/* Wait for PLL to Reset Properly */
426	mov	r10, $0xff
427
428ResetLoop:
429	subs	r10, r10, $1
430	bne	ResetLoop
431
432	/* Bring PLL out of Reset */
433	ldr	r6, PLL1_CTL
434	orr	r8, r8, $0x08
435	str	r8, [r6]
436
437	/* Wait for PLL to Lock */
438	ldr	r10, PLL_LOCK_COUNT
439
440PLL1Lock:
441	subs	r10, r10, $1
442	bne	PLL1Lock
443
444	/* Enable the PLL */
445	orr	r8, r8, $0x01
446	str	r8, [r6]
447
448	nop
449	nop
450	nop
451	nop
452
453	/*------------------------------------------------------*
454	 * AEMIF configuration for NOR Flash (double check)     *
455	 *------------------------------------------------------*/
456	ldr	r0, _PINMUX0
457	ldr	r1, _DEV_SETTING
458	str	r1, [r0]
459
460	ldr	r0, WAITCFG
461	ldr	r1, WAITCFG_VAL
462	ldr	r2, [r0]
463	orr	r2, r2, r1
464	str	r2, [r0]
465
466	ldr	r0, ACFG3
467	ldr	r1, ACFG3_VAL
468	ldr	r2, [r0]
469	and	r1, r2, r1
470	str	r1, [r0]
471
472	ldr	r0, ACFG4
473	ldr	r1, ACFG4_VAL
474	ldr	r2, [r0]
475	and	r1, r2, r1
476	str	r1, [r0]
477
478	ldr	r0, ACFG5
479	ldr	r1, ACFG5_VAL
480	ldr	r2, [r0]
481	and	r1, r2, r1
482	str	r1, [r0]
483
484	/*--------------------------------------*
485	 * VTP manual Calibration               *
486	 *--------------------------------------*/
487	ldr	r0, VTPIOCR
488	ldr	r1, VTP_MMR0
489	str	r1, [r0]
490
491	ldr	r0, VTPIOCR
492	ldr	r1, VTP_MMR1
493	str	r1, [r0]
494
495	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
496	ldr	r10, VTP_LOCK_COUNT
497VTPLock:
498	subs	r10, r10, $1
499	bne	VTPLock
500
501	ldr	r6, DFT_ENABLE
502	mov	r10, $0x01
503	str	r10, [r6]
504
505	ldr	r6, DDRVTPR
506	ldr	r7, [r6]
507	mov	r8, r7, LSL #32-10
508	mov	r8, r8, LSR #32-10        /* grab low 10 bits  */
509	ldr	r7, VTP_RECAL
510	orr	r8, r7, r8
511	ldr	r7, VTP_EN
512	orr	r8, r7, r8
513	str	r8, [r0]
514
515
516	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
517	ldr	r10, VTP_LOCK_COUNT
518VTP1Lock:
519	subs	r10, r10, $1
520	bne	VTP1Lock
521
522	ldr	r1, [r0]
523	ldr	r2, VTP_MASK
524	and	r2, r1, r2
525	str	r2, [r0]
526
527	ldr	r6, DFT_ENABLE
528	mov	r10, $0
529	str	r10, [r6]
530
531	/*
532	 * Call board-specific lowlevel init.
533	 * That MUST be present and THAT returns
534	 * back to arch calling code with "mov pc, lr."
535	 */
536	b	dv_board_init
537
538.ltorg
539
540_PINMUX0:
541	.word	0x01c40000		/* Device Configuration Registers */
542_PINMUX1:
543	.word	0x01c40004		/* Device Configuration Registers */
544
545_DEV_SETTING:
546	.word	0x00000c1f
547
548WAITCFG:
549	.word	0x01e00004
550WAITCFG_VAL:
551	.word	0
552ACFG3:
553	.word	0x01e00014
554ACFG3_VAL:
555	.word	0x3ffffffd
556ACFG4:
557	.word	0x01e00018
558ACFG4_VAL:
559	.word	0x3ffffffd
560ACFG5:
561	.word	0x01e0001c
562ACFG5_VAL:
563	.word	0x3ffffffd
564
565MDCTL_DDR2:
566	.word	0x01c41a34
567MDSTAT_DDR2:
568	.word	0x01c41834
569
570PTCMD:
571	.word	0x01c41120
572PTSTAT:
573	.word	0x01c41128
574
575EINT_ENABLE0:
576	.word	0x01c48018
577EINT_ENABLE1:
578	.word	0x01c4801c
579
580PSC_FLAG_CLEAR:
581	.word	0xffffffe0
582PSC_GEM_FLAG_CLEAR:
583	.word	0xfffffeff
584
585/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
586DDRCTL:
587	.word	0x200000e4
588DDRCTL_VAL:
589	.word	0x50006405
590SDREF:
591	.word	0x2000000c
592SDREF_VAL:
593	.word	0x000005c3
594SDCFG:
595	.word	0x20000008
596SDCFG_VAL:
597#ifdef	DDR_4BANKS
598	.word	0x00178622
599#elif defined DDR_8BANKS
600	.word	0x00178632
601#else
602#error "Unknown DDR configuration!!!"
603#endif
604SDTIM0:
605	.word	0x20000010
606SDTIM0_VAL_162MHz:
607	.word	0x28923211
608SDTIM1:
609	.word	0x20000014
610SDTIM1_VAL_162MHz:
611	.word	0x0016c722
612VTPIOCR:
613	.word	0x200000f0	/* VTP IO Control register */
614DDRVTPR:
615	.word	0x01c42030	/* DDR VPTR MMR */
616VTP_MMR0:
617	.word	0x201f
618VTP_MMR1:
619	.word	0xa01f
620DFT_ENABLE:
621	.word	0x01c4004c
622VTP_LOCK_COUNT:
623	.word	0x5b0
624VTP_MASK:
625	.word	0xffffdfff
626VTP_RECAL:
627	.word	0x08000
628VTP_EN:
629	.word	0x02000
630CFGTEST:
631	.word	0x80010000
632MASK_VAL:
633	.word	0x00000fff
634
635/* GEM Power Up & LPSC Control Register */
636MDCTL_GEM:
637	.word	0x01c41a9c
638MDSTAT_GEM:
639	.word	0x01c4189c
640
641/* For WDT reset chip bug */
642P1394:
643	.word	0x01c41a20
644
645PLL_CLKSRC_MASK:
646	.word	0xfffffeff	/* Mask the Clock Mode bit */
647PLL_ENSRC_MASK:
648	.word	0xffffffdf	/* Select the PLLEN source */
649PLL_BYPASS_MASK:
650	.word	0xfffffffe	/* Put the PLL in BYPASS */
651PLL_RESET_MASK:
652	.word	0xfffffff7	/* Put the PLL in Reset Mode */
653PLL_PWRUP_MASK:
654	.word	0xfffffffd	/* PLL Power up Mask Bit  */
655PLL_DISABLE_ENABLE_MASK:
656	.word	0xffffffef	/* Enable the PLL from Disable */
657PLL_LOCK_COUNT:
658	.word	0x2000
659
660/* PLL1-SYSTEM PLL MMRs */
661PLL1_CTL:
662	.word	0x01c40900
663PLL1_PLLM:
664	.word	0x01c40910
665
666/* PLL2-SYSTEM PLL MMRs */
667PLL2_CTL:
668	.word	0x01c40d00
669PLL2_PLLM:
670	.word	0x01c40d10
671PLL2_DIV1:
672	.word	0x01c40d18
673PLL2_DIV2:
674	.word	0x01c40d1c
675PLL2_PLLCMD:
676	.word	0x01c40d38
677PLL2_PLLSTAT:
678	.word	0x01c40d3c
679PLL2_DIV_MASK:
680	.word	0xffff7fff
681
682MMARG_BRF0:
683	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
684MMARG_BRF0_VAL:
685	.word	0x00444400
686
687DDR2_START_ADDR:
688	.word	0x80000000
689DUMMY_VAL:
690	.word	0xa55aa55a
691#else /* CONFIG_SOC_DM644X */
692	mov pc, lr
693#endif
694