1 /* 2 * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions. 3 * 4 * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> 5 * 6 * Based on drivers/usb/musb/davinci.h 7 * 8 * Copyright (C) 2009 Texas Instruments Incorporated 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 #ifndef __DA8XX_MUSB_H__ 13 #define __DA8XX_MUSB_H__ 14 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/gpio.h> 17 18 /* Base address of da8xx usb0 wrapper */ 19 #define DA8XX_USB_OTG_BASE 0x01E00000 20 21 /* Base address of da8xx musb core */ 22 #define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400) 23 24 /* Timeout for DA8xx usb module */ 25 #define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF 26 27 /* 28 * DA8xx platform USB wrapper register overlay. 29 */ 30 struct da8xx_usb_regs { 31 dv_reg revision; 32 dv_reg control; 33 dv_reg status; 34 dv_reg emulation; 35 dv_reg mode; 36 dv_reg autoreq; 37 dv_reg srpfixtime; 38 dv_reg teardown; 39 dv_reg intsrc; 40 dv_reg intsrc_set; 41 dv_reg intsrc_clr; 42 dv_reg intmsk; 43 dv_reg intmsk_set; 44 dv_reg intmsk_clr; 45 dv_reg intsrcmsk; 46 dv_reg eoi; 47 dv_reg intvector; 48 dv_reg grndis_size[4]; 49 }; 50 51 #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE) 52 53 /* DA8XX interrupt bits definitions */ 54 #define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ 55 #define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ 56 #define DA8XX_USB_TXINT_SHIFT 0 57 #define DA8XX_USB_RXINT_SHIFT 8 58 59 #define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ 60 #define DA8XX_USB_TXINT_MASK \ 61 (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT) 62 #define DA8XX_USB_RXINT_MASK \ 63 (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT) 64 65 /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ 66 #define CFGCHIP2_PHYCLKGD (1 << 17) 67 #define CFGCHIP2_VBUSSENSE (1 << 16) 68 #define CFGCHIP2_RESET (1 << 15) 69 #define CFGCHIP2_OTGMODE (3 << 13) 70 #define CFGCHIP2_NO_OVERRIDE (0 << 13) 71 #define CFGCHIP2_FORCE_HOST (1 << 13) 72 #define CFGCHIP2_FORCE_DEVICE (2 << 13) 73 #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) 74 #define CFGCHIP2_USB1PHYCLKMUX (1 << 12) 75 #define CFGCHIP2_USB2PHYCLKMUX (1 << 11) 76 #define CFGCHIP2_PHYPWRDN (1 << 10) 77 #define CFGCHIP2_OTGPWRDN (1 << 9) 78 #define CFGCHIP2_DATPOL (1 << 8) 79 #define CFGCHIP2_USB1SUSPENDM (1 << 7) 80 #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ 81 #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ 82 #define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ 83 #define CFGCHIP2_REFFREQ (0xf << 0) 84 #define CFGCHIP2_REFFREQ_12MHZ (1 << 0) 85 #define CFGCHIP2_REFFREQ_24MHZ (2 << 0) 86 #define CFGCHIP2_REFFREQ_48MHZ (3 << 0) 87 88 #define DA8XX_USB_VBUS_GPIO (1 << 15) 89 90 int usb_phy_on(void); 91 void usb_phy_off(void); 92 93 #endif /* __DA8XX_MUSB_H__ */ 94