1*3d357619SMasahiro Yamada /* 2*3d357619SMasahiro Yamada * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions. 3*3d357619SMasahiro Yamada * 4*3d357619SMasahiro Yamada * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> 5*3d357619SMasahiro Yamada * 6*3d357619SMasahiro Yamada * Based on drivers/usb/musb/davinci.h 7*3d357619SMasahiro Yamada * 8*3d357619SMasahiro Yamada * Copyright (C) 2009 Texas Instruments Incorporated 9*3d357619SMasahiro Yamada * 10*3d357619SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 11*3d357619SMasahiro Yamada */ 12*3d357619SMasahiro Yamada #ifndef __DA8XX_MUSB_H__ 13*3d357619SMasahiro Yamada #define __DA8XX_MUSB_H__ 14*3d357619SMasahiro Yamada 15*3d357619SMasahiro Yamada #include <asm/arch/hardware.h> 16*3d357619SMasahiro Yamada #include <asm/arch/gpio.h> 17*3d357619SMasahiro Yamada 18*3d357619SMasahiro Yamada /* Base address of da8xx usb0 wrapper */ 19*3d357619SMasahiro Yamada #define DA8XX_USB_OTG_BASE 0x01E00000 20*3d357619SMasahiro Yamada 21*3d357619SMasahiro Yamada /* Base address of da8xx musb core */ 22*3d357619SMasahiro Yamada #define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400) 23*3d357619SMasahiro Yamada 24*3d357619SMasahiro Yamada /* Timeout for DA8xx usb module */ 25*3d357619SMasahiro Yamada #define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF 26*3d357619SMasahiro Yamada 27*3d357619SMasahiro Yamada /* 28*3d357619SMasahiro Yamada * DA8xx platform USB wrapper register overlay. 29*3d357619SMasahiro Yamada */ 30*3d357619SMasahiro Yamada struct da8xx_usb_regs { 31*3d357619SMasahiro Yamada dv_reg revision; 32*3d357619SMasahiro Yamada dv_reg control; 33*3d357619SMasahiro Yamada dv_reg status; 34*3d357619SMasahiro Yamada dv_reg emulation; 35*3d357619SMasahiro Yamada dv_reg mode; 36*3d357619SMasahiro Yamada dv_reg autoreq; 37*3d357619SMasahiro Yamada dv_reg srpfixtime; 38*3d357619SMasahiro Yamada dv_reg teardown; 39*3d357619SMasahiro Yamada dv_reg intsrc; 40*3d357619SMasahiro Yamada dv_reg intsrc_set; 41*3d357619SMasahiro Yamada dv_reg intsrc_clr; 42*3d357619SMasahiro Yamada dv_reg intmsk; 43*3d357619SMasahiro Yamada dv_reg intmsk_set; 44*3d357619SMasahiro Yamada dv_reg intmsk_clr; 45*3d357619SMasahiro Yamada dv_reg intsrcmsk; 46*3d357619SMasahiro Yamada dv_reg eoi; 47*3d357619SMasahiro Yamada dv_reg intvector; 48*3d357619SMasahiro Yamada dv_reg grndis_size[4]; 49*3d357619SMasahiro Yamada }; 50*3d357619SMasahiro Yamada 51*3d357619SMasahiro Yamada #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE) 52*3d357619SMasahiro Yamada 53*3d357619SMasahiro Yamada /* DA8XX interrupt bits definitions */ 54*3d357619SMasahiro Yamada #define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ 55*3d357619SMasahiro Yamada #define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ 56*3d357619SMasahiro Yamada #define DA8XX_USB_TXINT_SHIFT 0 57*3d357619SMasahiro Yamada #define DA8XX_USB_RXINT_SHIFT 8 58*3d357619SMasahiro Yamada 59*3d357619SMasahiro Yamada #define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ 60*3d357619SMasahiro Yamada #define DA8XX_USB_TXINT_MASK \ 61*3d357619SMasahiro Yamada (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT) 62*3d357619SMasahiro Yamada #define DA8XX_USB_RXINT_MASK \ 63*3d357619SMasahiro Yamada (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT) 64*3d357619SMasahiro Yamada 65*3d357619SMasahiro Yamada /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ 66*3d357619SMasahiro Yamada #define CFGCHIP2_PHYCLKGD (1 << 17) 67*3d357619SMasahiro Yamada #define CFGCHIP2_VBUSSENSE (1 << 16) 68*3d357619SMasahiro Yamada #define CFGCHIP2_RESET (1 << 15) 69*3d357619SMasahiro Yamada #define CFGCHIP2_OTGMODE (3 << 13) 70*3d357619SMasahiro Yamada #define CFGCHIP2_NO_OVERRIDE (0 << 13) 71*3d357619SMasahiro Yamada #define CFGCHIP2_FORCE_HOST (1 << 13) 72*3d357619SMasahiro Yamada #define CFGCHIP2_FORCE_DEVICE (2 << 13) 73*3d357619SMasahiro Yamada #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) 74*3d357619SMasahiro Yamada #define CFGCHIP2_USB1PHYCLKMUX (1 << 12) 75*3d357619SMasahiro Yamada #define CFGCHIP2_USB2PHYCLKMUX (1 << 11) 76*3d357619SMasahiro Yamada #define CFGCHIP2_PHYPWRDN (1 << 10) 77*3d357619SMasahiro Yamada #define CFGCHIP2_OTGPWRDN (1 << 9) 78*3d357619SMasahiro Yamada #define CFGCHIP2_DATPOL (1 << 8) 79*3d357619SMasahiro Yamada #define CFGCHIP2_USB1SUSPENDM (1 << 7) 80*3d357619SMasahiro Yamada #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ 81*3d357619SMasahiro Yamada #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ 82*3d357619SMasahiro Yamada #define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ 83*3d357619SMasahiro Yamada #define CFGCHIP2_REFFREQ (0xf << 0) 84*3d357619SMasahiro Yamada #define CFGCHIP2_REFFREQ_12MHZ (1 << 0) 85*3d357619SMasahiro Yamada #define CFGCHIP2_REFFREQ_24MHZ (2 << 0) 86*3d357619SMasahiro Yamada #define CFGCHIP2_REFFREQ_48MHZ (3 << 0) 87*3d357619SMasahiro Yamada 88*3d357619SMasahiro Yamada #define DA8XX_USB_VBUS_GPIO (1 << 15) 89*3d357619SMasahiro Yamada 90*3d357619SMasahiro Yamada int usb_phy_on(void); 91*3d357619SMasahiro Yamada void usb_phy_off(void); 92*3d357619SMasahiro Yamada 93*3d357619SMasahiro Yamada #endif /* __DA8XX_MUSB_H__ */ 94