1*601fbec7SMasahiro Yamada /* 2*601fbec7SMasahiro Yamada * SoC-specific lowlevel code for DA850 3*601fbec7SMasahiro Yamada * 4*601fbec7SMasahiro Yamada * Copyright (C) 2011 5*601fbec7SMasahiro Yamada * Heiko Schocher, DENX Software Engineering, hs@denx.de. 6*601fbec7SMasahiro Yamada * 7*601fbec7SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 8*601fbec7SMasahiro Yamada */ 9*601fbec7SMasahiro Yamada #include <common.h> 10*601fbec7SMasahiro Yamada #include <nand.h> 11*601fbec7SMasahiro Yamada #include <ns16550.h> 12*601fbec7SMasahiro Yamada #include <post.h> 13*601fbec7SMasahiro Yamada #include <asm/arch/da850_lowlevel.h> 14*601fbec7SMasahiro Yamada #include <asm/arch/hardware.h> 15*601fbec7SMasahiro Yamada #include <asm/arch/davinci_misc.h> 16*601fbec7SMasahiro Yamada #include <asm/arch/ddr2_defs.h> 17*601fbec7SMasahiro Yamada #include <asm/ti-common/davinci_nand.h> 18*601fbec7SMasahiro Yamada #include <asm/arch/pll_defs.h> 19*601fbec7SMasahiro Yamada 20*601fbec7SMasahiro Yamada void davinci_enable_uart0(void) 21*601fbec7SMasahiro Yamada { 22*601fbec7SMasahiro Yamada lpsc_on(DAVINCI_LPSC_UART0); 23*601fbec7SMasahiro Yamada 24*601fbec7SMasahiro Yamada /* Bringup UART0 out of reset */ 25*601fbec7SMasahiro Yamada REG(UART0_PWREMU_MGMT) = 0x00006001; 26*601fbec7SMasahiro Yamada } 27*601fbec7SMasahiro Yamada 28*601fbec7SMasahiro Yamada #if defined(CONFIG_SYS_DA850_PLL_INIT) 29*601fbec7SMasahiro Yamada static void da850_waitloop(unsigned long loopcnt) 30*601fbec7SMasahiro Yamada { 31*601fbec7SMasahiro Yamada unsigned long i; 32*601fbec7SMasahiro Yamada 33*601fbec7SMasahiro Yamada for (i = 0; i < loopcnt; i++) 34*601fbec7SMasahiro Yamada asm(" NOP"); 35*601fbec7SMasahiro Yamada } 36*601fbec7SMasahiro Yamada 37*601fbec7SMasahiro Yamada static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) 38*601fbec7SMasahiro Yamada { 39*601fbec7SMasahiro Yamada if (reg == davinci_pllc0_regs) 40*601fbec7SMasahiro Yamada /* Unlock PLL registers. */ 41*601fbec7SMasahiro Yamada clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK); 42*601fbec7SMasahiro Yamada 43*601fbec7SMasahiro Yamada /* 44*601fbec7SMasahiro Yamada * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled 45*601fbec7SMasahiro Yamada * through MMR 46*601fbec7SMasahiro Yamada */ 47*601fbec7SMasahiro Yamada clrbits_le32(®->pllctl, PLLCTL_PLLENSRC); 48*601fbec7SMasahiro Yamada /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */ 49*601fbec7SMasahiro Yamada clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC); 50*601fbec7SMasahiro Yamada 51*601fbec7SMasahiro Yamada /* Set PLLEN=0 => PLL BYPASS MODE */ 52*601fbec7SMasahiro Yamada clrbits_le32(®->pllctl, PLLCTL_PLLEN); 53*601fbec7SMasahiro Yamada 54*601fbec7SMasahiro Yamada da850_waitloop(150); 55*601fbec7SMasahiro Yamada 56*601fbec7SMasahiro Yamada if (reg == davinci_pllc0_regs) { 57*601fbec7SMasahiro Yamada /* 58*601fbec7SMasahiro Yamada * Select the Clock Mode bit 8 as External Clock or On Chip 59*601fbec7SMasahiro Yamada * Oscilator 60*601fbec7SMasahiro Yamada */ 61*601fbec7SMasahiro Yamada dv_maskbits(®->pllctl, ~PLLCTL_RES_9); 62*601fbec7SMasahiro Yamada setbits_le32(®->pllctl, 63*601fbec7SMasahiro Yamada (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT)); 64*601fbec7SMasahiro Yamada } 65*601fbec7SMasahiro Yamada 66*601fbec7SMasahiro Yamada /* Clear PLLRST bit to reset the PLL */ 67*601fbec7SMasahiro Yamada clrbits_le32(®->pllctl, PLLCTL_PLLRST); 68*601fbec7SMasahiro Yamada 69*601fbec7SMasahiro Yamada /* Disable the PLL output */ 70*601fbec7SMasahiro Yamada setbits_le32(®->pllctl, PLLCTL_PLLDIS); 71*601fbec7SMasahiro Yamada 72*601fbec7SMasahiro Yamada /* PLL initialization sequence */ 73*601fbec7SMasahiro Yamada /* 74*601fbec7SMasahiro Yamada * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of 75*601fbec7SMasahiro Yamada * power down bit 76*601fbec7SMasahiro Yamada */ 77*601fbec7SMasahiro Yamada clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN); 78*601fbec7SMasahiro Yamada 79*601fbec7SMasahiro Yamada /* Enable the PLL from Disable Mode PLLDIS bit to 0 */ 80*601fbec7SMasahiro Yamada clrbits_le32(®->pllctl, PLLCTL_PLLDIS); 81*601fbec7SMasahiro Yamada 82*601fbec7SMasahiro Yamada #if defined(CONFIG_SYS_DA850_PLL0_PREDIV) 83*601fbec7SMasahiro Yamada /* program the prediv */ 84*601fbec7SMasahiro Yamada if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV) 85*601fbec7SMasahiro Yamada writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV), 86*601fbec7SMasahiro Yamada ®->prediv); 87*601fbec7SMasahiro Yamada #endif 88*601fbec7SMasahiro Yamada 89*601fbec7SMasahiro Yamada /* Program the required multiplier value in PLLM */ 90*601fbec7SMasahiro Yamada writel(pllmult, ®->pllm); 91*601fbec7SMasahiro Yamada 92*601fbec7SMasahiro Yamada /* program the postdiv */ 93*601fbec7SMasahiro Yamada if (reg == davinci_pllc0_regs) 94*601fbec7SMasahiro Yamada writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV), 95*601fbec7SMasahiro Yamada ®->postdiv); 96*601fbec7SMasahiro Yamada else 97*601fbec7SMasahiro Yamada writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV), 98*601fbec7SMasahiro Yamada ®->postdiv); 99*601fbec7SMasahiro Yamada 100*601fbec7SMasahiro Yamada /* 101*601fbec7SMasahiro Yamada * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that 102*601fbec7SMasahiro Yamada * no GO operation is currently in progress 103*601fbec7SMasahiro Yamada */ 104*601fbec7SMasahiro Yamada while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT) 105*601fbec7SMasahiro Yamada ; 106*601fbec7SMasahiro Yamada 107*601fbec7SMasahiro Yamada if (reg == davinci_pllc0_regs) { 108*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1); 109*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2); 110*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3); 111*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4); 112*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5); 113*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6); 114*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7); 115*601fbec7SMasahiro Yamada } else { 116*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1); 117*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2); 118*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3); 119*601fbec7SMasahiro Yamada } 120*601fbec7SMasahiro Yamada 121*601fbec7SMasahiro Yamada /* 122*601fbec7SMasahiro Yamada * Set the GOSET bit in PLLCMD to 1 to initiate a new divider 123*601fbec7SMasahiro Yamada * transition. 124*601fbec7SMasahiro Yamada */ 125*601fbec7SMasahiro Yamada setbits_le32(®->pllcmd, PLLCMD_GOSTAT); 126*601fbec7SMasahiro Yamada 127*601fbec7SMasahiro Yamada /* 128*601fbec7SMasahiro Yamada * Wait for the GOSTAT bit in PLLSTAT to clear to 0 129*601fbec7SMasahiro Yamada * (completion of phase alignment). 130*601fbec7SMasahiro Yamada */ 131*601fbec7SMasahiro Yamada while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT) 132*601fbec7SMasahiro Yamada ; 133*601fbec7SMasahiro Yamada 134*601fbec7SMasahiro Yamada /* Wait for PLL to reset properly. See PLL spec for PLL reset time */ 135*601fbec7SMasahiro Yamada da850_waitloop(200); 136*601fbec7SMasahiro Yamada 137*601fbec7SMasahiro Yamada /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */ 138*601fbec7SMasahiro Yamada setbits_le32(®->pllctl, PLLCTL_PLLRST); 139*601fbec7SMasahiro Yamada 140*601fbec7SMasahiro Yamada /* Wait for PLL to lock. See PLL spec for PLL lock time */ 141*601fbec7SMasahiro Yamada da850_waitloop(2400); 142*601fbec7SMasahiro Yamada 143*601fbec7SMasahiro Yamada /* 144*601fbec7SMasahiro Yamada * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass 145*601fbec7SMasahiro Yamada * mode 146*601fbec7SMasahiro Yamada */ 147*601fbec7SMasahiro Yamada setbits_le32(®->pllctl, PLLCTL_PLLEN); 148*601fbec7SMasahiro Yamada 149*601fbec7SMasahiro Yamada 150*601fbec7SMasahiro Yamada /* 151*601fbec7SMasahiro Yamada * clear EMIFA and EMIFB clock source settings, let them 152*601fbec7SMasahiro Yamada * run off SYSCLK 153*601fbec7SMasahiro Yamada */ 154*601fbec7SMasahiro Yamada if (reg == davinci_pllc0_regs) 155*601fbec7SMasahiro Yamada dv_maskbits(&davinci_syscfg_regs->cfgchip3, 156*601fbec7SMasahiro Yamada ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC)); 157*601fbec7SMasahiro Yamada 158*601fbec7SMasahiro Yamada return 0; 159*601fbec7SMasahiro Yamada } 160*601fbec7SMasahiro Yamada #endif /* CONFIG_SYS_DA850_PLL_INIT */ 161*601fbec7SMasahiro Yamada 162*601fbec7SMasahiro Yamada #if defined(CONFIG_SYS_DA850_DDR_INIT) 163*601fbec7SMasahiro Yamada static int da850_ddr_setup(void) 164*601fbec7SMasahiro Yamada { 165*601fbec7SMasahiro Yamada unsigned long tmp; 166*601fbec7SMasahiro Yamada 167*601fbec7SMasahiro Yamada /* Enable the Clock to DDR2/mDDR */ 168*601fbec7SMasahiro Yamada lpsc_on(DAVINCI_LPSC_DDR_EMIF); 169*601fbec7SMasahiro Yamada 170*601fbec7SMasahiro Yamada tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); 171*601fbec7SMasahiro Yamada if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) { 172*601fbec7SMasahiro Yamada /* Begin VTP Calibration */ 173*601fbec7SMasahiro Yamada clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); 174*601fbec7SMasahiro Yamada clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); 175*601fbec7SMasahiro Yamada setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); 176*601fbec7SMasahiro Yamada clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); 177*601fbec7SMasahiro Yamada setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); 178*601fbec7SMasahiro Yamada 179*601fbec7SMasahiro Yamada /* Polling READY bit to see when VTP calibration is done */ 180*601fbec7SMasahiro Yamada tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); 181*601fbec7SMasahiro Yamada while ((tmp & VTP_READY) != VTP_READY) 182*601fbec7SMasahiro Yamada tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); 183*601fbec7SMasahiro Yamada 184*601fbec7SMasahiro Yamada setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); 185*601fbec7SMasahiro Yamada setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); 186*601fbec7SMasahiro Yamada } 187*601fbec7SMasahiro Yamada setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); 188*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); 189*601fbec7SMasahiro Yamada 190*601fbec7SMasahiro Yamada if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { 191*601fbec7SMasahiro Yamada /* DDR2 */ 192*601fbec7SMasahiro Yamada clrbits_le32(&davinci_syscfg1_regs->ddr_slew, 193*601fbec7SMasahiro Yamada (1 << DDR_SLEW_DDR_PDENA_BIT) | 194*601fbec7SMasahiro Yamada (1 << DDR_SLEW_CMOSEN_BIT)); 195*601fbec7SMasahiro Yamada } else { 196*601fbec7SMasahiro Yamada /* MOBILE DDR */ 197*601fbec7SMasahiro Yamada setbits_le32(&davinci_syscfg1_regs->ddr_slew, 198*601fbec7SMasahiro Yamada (1 << DDR_SLEW_DDR_PDENA_BIT) | 199*601fbec7SMasahiro Yamada (1 << DDR_SLEW_CMOSEN_BIT)); 200*601fbec7SMasahiro Yamada } 201*601fbec7SMasahiro Yamada 202*601fbec7SMasahiro Yamada /* 203*601fbec7SMasahiro Yamada * SDRAM Configuration Register (SDCR): 204*601fbec7SMasahiro Yamada * First set the BOOTUNLOCK bit to make configuration bits 205*601fbec7SMasahiro Yamada * writeable. 206*601fbec7SMasahiro Yamada */ 207*601fbec7SMasahiro Yamada setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK); 208*601fbec7SMasahiro Yamada 209*601fbec7SMasahiro Yamada /* 210*601fbec7SMasahiro Yamada * Write the new value of these bits and clear BOOTUNLOCK. 211*601fbec7SMasahiro Yamada * At the same time, set the TIMUNLOCK bit to allow changing 212*601fbec7SMasahiro Yamada * the timing registers 213*601fbec7SMasahiro Yamada */ 214*601fbec7SMasahiro Yamada tmp = CONFIG_SYS_DA850_DDR2_SDBCR; 215*601fbec7SMasahiro Yamada tmp &= ~DV_DDR_BOOTUNLOCK; 216*601fbec7SMasahiro Yamada tmp |= DV_DDR_TIMUNLOCK; 217*601fbec7SMasahiro Yamada writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); 218*601fbec7SMasahiro Yamada 219*601fbec7SMasahiro Yamada /* write memory configuration and timing */ 220*601fbec7SMasahiro Yamada if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { 221*601fbec7SMasahiro Yamada /* MOBILE DDR only*/ 222*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_DDR2_SDBCR2, 223*601fbec7SMasahiro Yamada &dv_ddr2_regs_ctrl->sdbcr2); 224*601fbec7SMasahiro Yamada } 225*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); 226*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); 227*601fbec7SMasahiro Yamada 228*601fbec7SMasahiro Yamada /* clear the TIMUNLOCK bit and write the value of the CL field */ 229*601fbec7SMasahiro Yamada tmp &= ~DV_DDR_TIMUNLOCK; 230*601fbec7SMasahiro Yamada writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); 231*601fbec7SMasahiro Yamada 232*601fbec7SMasahiro Yamada /* 233*601fbec7SMasahiro Yamada * LPMODEN and MCLKSTOPEN must be set! 234*601fbec7SMasahiro Yamada * Without this bits set, PSC don;t switch states !! 235*601fbec7SMasahiro Yamada */ 236*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_DDR2_SDRCR | 237*601fbec7SMasahiro Yamada (1 << DV_DDR_SRCR_LPMODEN_SHIFT) | 238*601fbec7SMasahiro Yamada (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT), 239*601fbec7SMasahiro Yamada &dv_ddr2_regs_ctrl->sdrcr); 240*601fbec7SMasahiro Yamada 241*601fbec7SMasahiro Yamada /* SyncReset the Clock to EMIF3A SDRAM */ 242*601fbec7SMasahiro Yamada lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); 243*601fbec7SMasahiro Yamada /* Enable the Clock to EMIF3A SDRAM */ 244*601fbec7SMasahiro Yamada lpsc_on(DAVINCI_LPSC_DDR_EMIF); 245*601fbec7SMasahiro Yamada 246*601fbec7SMasahiro Yamada /* disable self refresh */ 247*601fbec7SMasahiro Yamada clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 248*601fbec7SMasahiro Yamada DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); 249*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); 250*601fbec7SMasahiro Yamada 251*601fbec7SMasahiro Yamada return 0; 252*601fbec7SMasahiro Yamada } 253*601fbec7SMasahiro Yamada #endif /* CONFIG_SYS_DA850_DDR_INIT */ 254*601fbec7SMasahiro Yamada 255*601fbec7SMasahiro Yamada __attribute__((weak)) 256*601fbec7SMasahiro Yamada void board_gpio_init(void) 257*601fbec7SMasahiro Yamada { 258*601fbec7SMasahiro Yamada return; 259*601fbec7SMasahiro Yamada } 260*601fbec7SMasahiro Yamada 261*601fbec7SMasahiro Yamada int arch_cpu_init(void) 262*601fbec7SMasahiro Yamada { 263*601fbec7SMasahiro Yamada /* Unlock kick registers */ 264*601fbec7SMasahiro Yamada writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); 265*601fbec7SMasahiro Yamada writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); 266*601fbec7SMasahiro Yamada 267*601fbec7SMasahiro Yamada dv_maskbits(&davinci_syscfg_regs->suspsrc, 268*601fbec7SMasahiro Yamada CONFIG_SYS_DA850_SYSCFG_SUSPSRC); 269*601fbec7SMasahiro Yamada 270*601fbec7SMasahiro Yamada /* configure pinmux settings */ 271*601fbec7SMasahiro Yamada if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) 272*601fbec7SMasahiro Yamada return 1; 273*601fbec7SMasahiro Yamada 274*601fbec7SMasahiro Yamada #if defined(CONFIG_SYS_DA850_PLL_INIT) 275*601fbec7SMasahiro Yamada /* PLL setup */ 276*601fbec7SMasahiro Yamada da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); 277*601fbec7SMasahiro Yamada da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM); 278*601fbec7SMasahiro Yamada #endif 279*601fbec7SMasahiro Yamada /* setup CSn config */ 280*601fbec7SMasahiro Yamada #if defined(CONFIG_SYS_DA850_CS2CFG) 281*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr); 282*601fbec7SMasahiro Yamada #endif 283*601fbec7SMasahiro Yamada #if defined(CONFIG_SYS_DA850_CS3CFG) 284*601fbec7SMasahiro Yamada writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr); 285*601fbec7SMasahiro Yamada #endif 286*601fbec7SMasahiro Yamada 287*601fbec7SMasahiro Yamada da8xx_configure_lpsc_items(lpsc, lpsc_size); 288*601fbec7SMasahiro Yamada 289*601fbec7SMasahiro Yamada /* GPIO setup */ 290*601fbec7SMasahiro Yamada board_gpio_init(); 291*601fbec7SMasahiro Yamada 292*601fbec7SMasahiro Yamada 293*601fbec7SMasahiro Yamada NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), 294*601fbec7SMasahiro Yamada CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); 295*601fbec7SMasahiro Yamada 296*601fbec7SMasahiro Yamada /* 297*601fbec7SMasahiro Yamada * Fix Power and Emulation Management Register 298*601fbec7SMasahiro Yamada * see sprufw3a.pdf page 37 Table 24 299*601fbec7SMasahiro Yamada */ 300*601fbec7SMasahiro Yamada writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 301*601fbec7SMasahiro Yamada DAVINCI_UART_PWREMU_MGMT_UTRST), 302*601fbec7SMasahiro Yamada #if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) 303*601fbec7SMasahiro Yamada &davinci_uart0_ctrl_regs->pwremu_mgmt); 304*601fbec7SMasahiro Yamada #else 305*601fbec7SMasahiro Yamada &davinci_uart2_ctrl_regs->pwremu_mgmt); 306*601fbec7SMasahiro Yamada #endif 307*601fbec7SMasahiro Yamada 308*601fbec7SMasahiro Yamada #if defined(CONFIG_SYS_DA850_DDR_INIT) 309*601fbec7SMasahiro Yamada da850_ddr_setup(); 310*601fbec7SMasahiro Yamada #endif 311*601fbec7SMasahiro Yamada 312*601fbec7SMasahiro Yamada return 0; 313*601fbec7SMasahiro Yamada } 314